Single Phase Asymmetrical Cascaded MLI with Extreme Output Voltage Levels to Switch Ratio

This paper proposes an asymmetrical cascaded single phase H-bridge inverter. The proposed inverter consists of two modules with unequal and isolated dc sources. Each module is composed of dc source, conventional four switches H-bridge and single bidirectional switch. To increase the output voltage levels, the tertiary ratio, 1:3, between its two dc sources is adopted. Both the fundamental frequency and the multicarrier pulse width modulation (PWM) control schemes are employed to generate switches signals. By controlling the inverter modulation index, the proposed inverter can generate an output voltage having up to seventeen levels by using only two modules. The proposed topology has also the feature of modularity which means that it can be extended to any levels by adding new modules. The proposed topology is simulated using an inductive load and some selected simulation results have been provided to validate the proposed inverter. Keyword: Cascaded Multilevel inverter; symmetrical and asymmetrical configuration; Pulse width modulation; Fundamental frequency control; Selective harmonic elimination (SHE).


INTRODUCTION
Multilevel inverters (MLIs) have gained grate interests in power electronics conversions techniques in the recent years. MLIs are preferred to conventional two level inverters due to (a) they can generate an output voltage which is very close to the sinusoidal waveform and thus they are considered as high power quality systems, (b) they can operate at low switching frequency with high quality output waveforms due to the increased levels and therefore switches stresses and electromagnetic interference can be diminished. The first MLI is the neutral point clamped topology [1]. Generally there are three main MLIs, diode-clamped, flying-capacitor, and cascaded H-bridge (CHB) [2][3] .
Generally the CHB MLI consists of a number of conventional H-bridge inverter modules. Each H-bridge module can generate three levels (0, Vdc, -Vdc). These H-bridge modules are generally connected in series and the final output voltage is synthesized by the combination of theseH-bridge modules. The CHB has the advantage of simple control and structure due to the modular characteristic. Therefore, it is very easy to replace any module if it becomes faulty. Even without discontinuing the load, it is possible to bypass the faulty module by applying an suitable control technique [4 -6].
The CHB inverter can be divided into two main groups; symmetric and asymmetric or hybrid. The output voltage levels of asymmetric per arm that can be generated are 2n+1where 'n' is the number of H-bridge series connected modules. On the other hand, the most well-known ratios for asymmetric are binary and tertiary, they can generate2(n+1)-1voltage levels per arm. Therefore the asymmetric MLI can reduce the size and cost of the system and improve the reliability due to using fewer semiconductors and capacitors.
A single-phase 7-level PWM inverter is proposed in [7]which synthesizes seven voltage levels per cycle (0, Vdc, 2Vdc, 3Vdc, -Vdc, -2Vdc, 3 Vdc). This inverter nearly triples the output voltage levels and thus its output voltage harmonic contents are reduced compared to the conventional H-bridge inverter. In [8], authors added a bidirectional switch to the conventional H-bridge single phase inverter. Therefore a five level output voltage waveform. In [9] authors used two series similar modules of the inverter proposed in [8] with equal dc sources. Thus that topology can generate 9 levels (0, Vdc, 2Vdc,3Vdc, 4Vdc, -Vdc, -2Vdc, -3 Vdc, -4Vdc) and it is considered as a symmetric MLI. In this proposed topology an asymmetrical CHB inverter based on [8] and [9]is presented. Instead of using equal dc sources, the tertiary ratio is employed to increase the voltage levels with the same number of switches. The number of output voltage levels is increased to 17. The presented MLI in this paper is a modular in addition to both fundamental frequency and PWM control schemes can be employed. Simulation results are provided to verify the validity of the proposed system The paper is organized as follows: section 2 gives the operational principles of the proposed MLI topology. The Modulation Techniques for the proposed MLI is presented in section 3. Subsequently simulation results are provided in section 4. Modularity of the proposed topology has been studied in section 5. Section 6 presents a comparison between the proposed topology and existing counterparts MLI topologies. Finally conclusion is presented in section 7. Figure 1(a), (b) and (c) shows the proposed 17 levels single phase asymmetrical cascaded inverter topology and its generated output voltage waveforms for low and medium modulation index ( ). The proposed inverter consists of two series connected modules based on [9]. Each module consists of five IGBT switches as well as four main diodes. Each module requires two equal and non-isolated dc sources. To increase the levels of output voltage, a tertiary ratio 1:3 between the upper module dc source (2 ) and the lower module dc source (6 ) is adopted. It can be noted that, the input voltage for each module is divided into two equal voltages as shown in figure 1. To obtain this number of levels from the conventional topologies like cascaded H-bridge (CHB) [10], neutral point clamped (NPC) [11], or flying capacitor (FC) inverters [12], a large number of switches and diodes have to be used. The main advantages of the proposed topology are; (1) high level switch ratio (LSR) [13] because of using unequal DC voltage values (1:3 dc source ratio) resulting in reducing the number of components used; (2) the switches utilized in upper module with lower dc source value operate at switching frequency, while the switches utilized in lower module with higher dc source value operate at low frequency. Consequently the switches losses will be reduced.

OPERATIONAL PRINCIPLES OF ASYMMETRICAL CASCADED MLI TOPOLOGY
The generated output voltage levels of the proposed MLI are shown in Table 1 where two modules are considered with 10 switches and 4 diodes that are able to generate 17 output voltage levels. The lower module dc voltage source is three times the upper module dc voltage source. From Table 1, to achieve any level, four switches have to be turned on. As an example, for the first level Q4, Qa, Q7, and Q8should be turned on to get in the output. In this case, inverter voltage = =vo,1. It could be noticed from figure 1 (b) and (c) that as the modulation index increases, more levels are generated.

MODULATION TECHNIQUES FOR THE PROPOSED MLI
Modulation techniques for MLI can be divided into two wellknown categories depending on the switching frequency used to drive the inverter switches: (a) fundamental frequency modulation technique, (b) Sinusoidal Pulse-width modulation (SPWM) technique. Fortunately the proposed topology can be controlled and implemented using both control schemes as explained in details in the following paper section.

(A) FUNDAMENTAL FREQUENCY CONTROL SCHEME
The fundamental frequency control technique is very efficient for MLI because of its superior performance in reducing switching losses and stresses especially in case of using many switches like this proposed MLI. In this case either selective harmonic elimination (SHE) or harmonic minimization technique can be used to determine the switching angles of different switches. Eq. (1) defines the modulation index, it is defined as the output ac fundamental frequency voltage divided by the total dc voltage. For very low , a three levels output voltage waveforms (0, , -) is constructedsimilar to the conventional H-bridge inverter. As the increases, the inverter generated levels increases. Eqs. (2) and (3) give the fundamental voltage of both cases of in figure 1(b) and (c). Eqs. (4) and (5) give the harmonic voltage of the same two cases. It could be noticed that for high , an eight switching angles will be emerged and need to be solved. Also as the modulation index increases the switching angles ( 1 , 2 , …) increase. The general equation of the harmonic components for the eight switching angles is given in Eq. 6.
(b) Generated output voltage for low modulation index.
(c) Generated output voltage for medium modulation index.
Where 0 < 1 < 2 < 3 < 4 < 5 < 6 < 7 < 8 < 2 The total harmonic distortion (THD) can be calculated as in Eq. (7) In SHE technique, lower order harmonics are selected to be cancelled based on how many switching angles are exist. But in harmonic elimination technique the solution of the switching angles ( 1 , 2 , …) are generated based on minimizing the value of THD of Eq. (6). It can be noticed that either in SHE technique or THD minimizing technique, the above equations can be solved using iteration method such as Newton Raphson or secant search engine [14 -16] to satisfy the fundamental voltage and cancel lower harmonics up to 7 orders at the same time. Table 2 provides the lookup table  solution for different modulation indexes. It could be noticed that the higher the modulation index ( ) the higher the number of voltage levels are required to achieve the inverter output voltage command. Also the percentage THD of the inverter output voltage decreases rapidly as the modulation index increases. Figures 2(a) and 2(b) give the lower order harmonics beside the fundamental voltage with changing modulation index. In case of very low modulation indexes at 0.1 and 0.2, the lower order harmonics especially the 3 rd , 5 th and 7 th have significant values as compared to the fundamental because the behavior of the proposed MLI is typically similar to conventional two levels inverter. For other modulation indexes greater than or equal 0.3, more output voltage levels will appear and consequently more lower order harmonics can be cancelled. For example = 0.7 lower harmonic orders 3 rd , 5 th ,7 th , 9 th are almost vanished.
Although fundamental frequency control scheme has many advantages as previously described, it has some drawbacks. Equations solution of the SHE technique is the main disadvantages of this method because it is a very complex and tedious work in addition the solution is not satisfied at certain modulation indexes. Thus applying this technique will lead to discontinuous range of control.

(B) PWM CONTROL SCHEME
The proposed MLI can also be controlled using the wellknown sinusoidal pulse width modulation (SPWM) control scheme. SPWM control scheme advantage is that it has a continuous control range of modulation indexes. In SPWM control scheme a number of carriers signals are compared with a rectified sinusoidal signal with amplitude ( ) to generate the inverter control signals. Eq. (8) gives the modulating signal. In the proposed MLI, 8 carrier signals with same magnitude ( ) and frequency but shifted by a dc level from each other. This shifted dc level equals to the carrier magnitude ( ). Boolean signals are generated from this comparison and thus the switches control pulses can be generated.
The comparison generates 8 signals ( , , , , , , , ℎ ) with low frequency and 8 signals ( , , , , , , , ℎ ) with switching frequency. In addition, zero crossing two signals P & N are generated from comparing the modulating sinusoidal signal with a zero dc value. Figure 3 (a) depicts the 8 carriers and the rectified sinusoidal signal. Figure 3(b) shows the 8 low frequency signals while figure 4(c) provides the 8 high frequency signals. Eq. (9) gives switches on/off control Boolean formula. As explained before the output voltage levels increases with increasing modulation index and its percentage THD decreases rapidly with increasing too as shown in Figure 4.

SIMULATION RESULTS
In this section, simulation results are illustrated for both low frequency and SPWM control schemes. The proposed MLI has been built and simulated using MATALB/Simulink package. The dc input voltage are =40V. In addition, the load is R-L with L=100mH and R=30.Furthermore, in case of SPWM control scheme, the employed switching frequency is2kHz. Some selected results are provided to validate the proposed system. Figure 5 shows the low frequency control scheme results for simulation. The studied cases are chosen to cover wide range of modulation indexes, they are = 0.2, 0.5, and 0.9. In this control method, the selected harmonic elimination technique is employed to fix the fundamental frequency and at the same time to cancel lower order harmonics. For example, for = 0.2, there are two steps in the output voltage and therefore it can attain the fundamental frequency voltage at a constant value and cancel only the third harmonic as shown in figure 5 (a) and 5 (d). For large , higher number of lower order harmonics can be cancelled as shown in figure 5(b) and 5(e) where third, fifth and seventh harmonics are cancelled. Also for = 0.9 as illustrated in figure 5(c) and 5(f) all lower order harmonics are cancelled or become less than 3% which can be considered negligible. Figure 6 shows the SPWM simulation results. Also the studied cases are chosen to cover wide range of modulation indexes, they are = 0.2, 0.5, and 0.9 at switching frequency 2 kHz.
These aforementioned figures validate the proposed SPWM control scheme for the proposed topology and confirm that the proposed MLI can be considered as a high performance MLI from the point of view of power electronic components used because it can generate up to 17 voltage levels using only 10 power switches in addition 8 main diodes. Consequently the level-switch ratio (LSR) is 1.7. Figure 7 illustrates the output voltage of upper and lower modules in case of SPWM control at = 0.9. It can be noticed that upper module switches operate at the switching frequency and low voltage. On the other hand, lower module switches operate at almost power frequency and high voltage. Moreover control signals of switches are shown in figure 8 where upper and lower module switches operate at switching frequencies as previously described. Thus the overall losses of the switches could be reduced and this is one of the main advantages of the proposed MLI.

PROPOSED MLI MODULARITY
The proposed topology in this paper has a modular performance; therefore other modules can be added to figure 1 without changing the main inverter configuration. As a result more levels can be achieved. The ratio among the input dc voltage of inverter modules is 2:6:18: …, which means the general ratio of the inverter is 1:3. Assuming that the output voltages of the modules are 1 , 2 , 3 , … , , the inverter output voltage is given by: The number of switches Nswitch and the number of the diodes Ndiodes are giving by the following equations Ndiodes= 4×n (12) Where n is the number of inverter modules. The number of the output voltage levels is varying according to the symmetrical or asymmetrical voltage. The number of the output voltage levels NLevels for symmetrical and asymmetrical structure is calculated as follows:

COMPARISON BETWEENTHE PROPOSED MLI AND EXISTING MLI
Comparison between the proposed MLI topology and other existing counterparts MLI topologies have been done in this section. The comparison considers switches number, number of main diodes, output voltage levels, types of MLI configuration, switches voltage stresses and THD performance of output voltage waveform. For fair comparison between the proposed topology and its counterparts existence topologies, the output peak voltage is assumed to be fixed at . The number of the output voltage levels of the proposed topology is about twice that of symmetrical scheme [9]. This comparison is given in Table 3 and it reveals that the proposed topology has higher LSR and less switches voltage stresses. It also has high performance due to low THD value.

CONCLUSION
In this paper, a new asymmetrical cascaded seventeen levels single-phase inverter is proposed. The proposed inverter has extreme levels to switch ratio (LSR) which reaches 1.7 in addition, the proposed MLI is considered as a modular which means it can be extended by adding more modules to achieve more output voltage levels. The proposed inverter operational principles and switches times diagram have been provided. Both fundamental frequency and the multicarrier PWM control techniques have been employed to generate switches pulses. Half of the proposed MLI switches operate at the switching frequency and at low voltage while the other half switches turn on and off at almost power frequency and at high voltage. Consequently the MLI switching losses is decreased. The performance of the proposed topology has been validated using simulation results for an inductive load. The output voltage THD shows that it has as low as 5.2%.  Table 3.Comparison between the proposed MLI topology and two other systems for fixed peak output voltage.