Design of new power generating circuit for passive UHF RFID tag

In this paper, we propose a new power generating circuit for passive ultra high frequency (UHF) RFID tag. The proposed power generating circuit consists of a RF limiter, a high power efficiency and high sensitivity full wave radio frequency (RF) wave rectifier and a low-power regulator with NMOS diodes work like a DC-limiter. The design method proposed in this study use one low drop out (LDO) regulator to provide tow output stable supply voltages vdd1 of value 1V for the digital section supply, and vdd2 of value 0.5V for the analog front-end section power supply. The proposed power generating circuit is optimized in terms of power consumption of RFID tag system to have a high operating range under conditions of 50 Ohm antenna, -24 dBm input RF power, 900MHz and 1 M DC, with low power dissipation and 29.15% large power conversion efficiency. The power generating circuit was designed, simulated and layouted in Cadence using TSMC 180 nm technology. The final design occupies approximately 0.25mm2.


INTRODUCTION
RFID (radio frequency identification) it is a technology uses electromagnetic waves to transmit the ID of objects. It is a technology operates in non line of sight environments. RFID technology is becoming a part of our every life, at work in supermarkets at home and it can be implanted in animal or human bodies [1]. An RFID system consists of three main elements, an RFID tag/transponder, a reader or a transceiver contains an antenna and an electronic circuit that emits an electromagnetic wave (power) to active the passive RFID tag and a host system. In general, there are three types of RFID tags, an active tag, a semi active tag (semi passive tag) and a passive tag whiche powered from the received RF signal [2]. One of the most parameters to determine the communication range of the RFID system is the frequency. In the ultra-high frequency range frequencies can vary from 433 MHz to 2.45 GHz. frequency depends on location; for example, 868 MHz is only used in Europe, when 900 to 928 MHz is used in Canada and the USA.
The ultra high frequency (UHF) passive RFID tags have many advantages like their low cost, their low power consumption, their longer distance of operation, small antenna size and high data rate [3].
The principle of working of passive transponder is as follows, the demodulator extracts the amplitude shift keying (ASK) signal and demodulated form the baseband processor. The voltage rectifier circuit converts the received radio frequency (RF) signal from the antenna into a sufficiently DC voltage Vr, this later is regulated by a voltage regulator circuit to generate a stable voltage supply to other sub-blocks of 1390 the tag. The baseband processor manipulates the received binary data and then generates outputs according to the operations of the tag. Modulation tequhnique is done (using ASK modulation) by varing the effective impedance of the antenna to backscatter signals back to the tranciever. The block diagram of a UHF RFID transponder is shown in Figure 1, it consists of an antenna, a digital part, and an analog front-end part contains, a modulator, a demodulator and an oscillator. For each analog front-end passive RFID tag we have a power generating circuit that can generate the power to each RFID tag sub-blocks. The efficiency of power generating circuit and communication range d of the RFID system depend on the voltage rectifier used in the voltage generator circuit. The Friss transmission (1) gives us the theoretical communication range d [4].

Where
, , , and are the free space wavelength, the effective isotropic radiated power of a reader, the gain of the tag antenna, the practicable operating power of an RFID tag is the power conversion efficiency of the rectifier used in the power generation circuit respectively.
The main chalanges in RFID technology are: the minimizing of the power consumption of RFID tag, the incrasing of the communication distance and the efficiency of voltage regulation. Many works was interested by the designing of the power generating circuit. Voltage rectifier with high power efficiency augments both the efficiency of the voltage regulation circuit and communication range d of RFID system. A voltage rectifier using Schottky diodes and capacitors has many advantages like their low junction capacitance, their small series resistance. Because of its less expensive and more compatible with standard CMOS technologies native NMOS transistor used in works [5], [6] and [7] is used instead Schottky diodes used in [8]. Both schottky diodes and native NMOS transistor rectifiers have many disadvantages; one of the common disadvantages of such rectifiers is the drop voltage of the output because of MOS transistors threshold voltage. The threshold voltage, not only reduces the power efficiency, but also decreases the output rectified voltage.
So to minimize the power consumption of the transponder and to incrase the communication distance of RFID system, we propose a new aproach wihich the RFID tag consumes a low power compared with other recent researches and with longer communication distance. In this aproach we propose a low power voltage regulation circuit with tow supply voltages from one low droup out (LDO) regulator using a new full wave RF rectifier whiche have advantages compared with schotky diodes and native NMOS transistor rectifiers, with the aim of eliminating the effect of threshold voltage of the pass transistor. The cross-coupled structure in voltage rectifier is considered for NMOS pass transistors and the capacitor and the transistor is used as the bootstrap circuit for neutralizing the effect of the PMOS pass transistors threshold voltage, which leads to reducing the chip area. In order to minimize the power consumption, we propose the reducing of the supply voltage of the analog section of a 0.5V while maintaining a supply voltage 1V to the digital core, using a new full wave RF rectifier with a high power efficiency and high sensitivity will incrase the communication distance. The analog front-end section shown in Figure 1 wihich consists of proposed power generation circuit whiche generates two output voltages using one LDO regulator with multiple output vdd1and vdd2 their values are stable. vdd2 gets the power supply to the analog sub-blocks (modulator, demodulator, clock generator, ring oscillator), its value 0.5V. vdd1 generates a supply voltage to the digital sub-blocks (control logic and ROM), its value is 1V. The proposed generating circuit proposed in this paper was designed in 180 nm CMOS process whiche consists of an RF voltage limiter circuit (protector) this later can protect the transponder system from damages caused to CMOS gate-oxide breakdown due to an excessive coupling voltage from the reader for a short operating distance. A high power efficiency and high sensitivity full wave RF wave rectifier is used to convert the RF received power to DC signals; the full wave rectifier is fully integrable and takes advantage of both passive and active multiplications to reduce the required input power. The minimum required input power is -24 dBm to generate supply voltage from a 50-Ohm antenna at 900 MHz, and a voltage regulator which regulates the output voltage of the rectifier to a preferd value.

POWER GENERATING CIRCUIT
The proposed power generating circuit consists of an RF voltage limiter, a high power efficiency and high sensitivity full wave rectifier and a voltage regulator. Theoretical analyzes and simulations of the circuits used to optimize the design are presented. The circuit shows the ability to generate stable DC voltages independent of the input power levels and it can be powered the passive UHF RFID tag. In this section, each sub-block of voltage regulation circuit is presented with more details.

Voltage RF limiter
The voltage at the input of the voltage rectifier can goes from 350 mV to 20 V, depending on the proximity of the tag. To prevent the transistors of the inner circuit from being damaged at high voltage levels an RF limiter is used. The RF signal is detected by the RF_in of the RF voltage limiter which is a stacked voltage diode referenced to the ground of the RFID tag. The output of RF limiter is given by (2): With K′ and V are transconductance parameter and the threshold voltage of PMOS transistor respectively. In (2) the value in the square root is minimized by using large transistor aspect ratios of transistors, with the Id we can write: This means that when the RF signal exceeds 2 V , the RF voltage will reduce the actual voltage, above 2 V , the additional voltage appearing at the gate of NMOS transistor N1. After a certain limit of the transistor, N1 gradually turns on. Once N1 is fully activated, PMOS transistor P3 starts to decrease. To prevent the RF signal from being completely limited, a resistor R3 is used to maintain a voltage drop on the RF signal and N1 drain. When the gate voltage of P3 continues to drop as a result of switching N1, P3 starts to turn on. At this time, transistor P3 acts as a shunt and limits the increase of any applied RF signal. Figure 3 shows the amplitude of input signal after usin proposed voltage limiter.

Fulle wave RF rectifier
The voltage rectifier is a circuit converts the RF incident signal to a DC signal with very small ripples. It comes after the RF voltage limiter.
To improve power efficiency, the proposed full wave RF rectifier shown in Figure 6 uses the combination of the bootstrap circuit (capacitor and transistor ) with the cross-coupled structure [9].Transistors , .
, and are replaced by the transistors connected on diode of the conventional bridge rectifier and conduct the current path from the input source to the output load. Transistors M and with the cross-coupled structure have the channel resistivity lower than their activation time. To improve the efficiency and the output voltage, the bootstrap is used to cancel the threshold voltage of the PMOS transistors. The the bootstrap circuit is built using the capacitor with transistor . In this proposed topology, the gates of the transistors and and are connected to each other (transistors connected on diode), the gats of transistors are connected with the output of the voltage rectifier to reduce the effect of the threshold voltage of and , PMOS pass transistors. The current of the input source charges boths the output capacitor and the capacitor by and . The voltage accros the capacitor can be suitable for the complete conductivity of the PMOS pass transistors. To reduce the leakage current, the sizes of the positive half-cycle, when the input voltage (V ) is larger than the output voltage, the current loads the output capacitor by M , the transistor connected to the diode. The voltage of the output capacitor and the capacitor C is given as follows: (6) and (15).
The voltage across the capacitor , activates the transistor to simultaneously charge the capacitor with the transistor . The voltage V_GS of transistor is: V of M is equal to its threshold voltage the transistor M is deactivated when, so we can write: Using (7) and (9), the output voltage can be calculated from (10).
Therefore, if | | | |, the capacitor is charged on the value equal to the input voltage. The tow PMOS, and diode transistors operate in a dynamic region have a ground (bulk) terminal that is not connected to the high voltage during a complete cycle. This problem causes the increase of the threshold voltage of the transistors connected to the diode and the bulk leakage current. The bulk bias circuit ( , , , and ) is used to eliminate the body effect of transistors and . Since the effect of the threshold voltage of transistors and is neutralized by the bootstrap, the bulk bias circuit does not use for and , in order to have the maximum output voltage. Thus, the body of such transistors is connected to V . The power conversion efficiency of proposed rectifier is given by (11).
With (12) Where P_OUT and P_IN are the output power and input incident power respectively. Figure

Regulator
The regulator circuit comes after the full wave rectifier. The voltage regulator performs two main functions. The first is to regulate the output voltage to a preferred value and a preferred range for passive RFID UHF tag. The other is to protect the inner circuits from breaking at high RF input power. The basic topology of a voltage regulator is shown in Figure 8. It consists of on OTA, tow regulation resistances and a voltage reference to generate a regulated voltage [10].
The output of a voltage regulator V is given as follow. In an ideal case considering a finite openloop gain A_ol the regulated voltage is given by: we can write: .
If we consider an infinite open-loop gain for an ideal case so the simplifying calculates can we give: In (16) the output voltage of voltage regulator depends on the voltage reference and resistance and .  The NMOS diode regulator uses four series diode connected native NMOS transistor to limit large output of the voltage rectifier, which is on the order of dozens of tens of volts, to a relatively small swing.
One of characteristic of RFID passive tags is the fully integrated, RFID tag has not an external voltage reference, it means that the voltage reference used in voltage reference must be auto generated, even the power supply voltage. As shown in Figure 7, 1.6 V is generated directly by a reference self-biased voltage, instead of the conventional method for amplifying a low-precision reference voltage of the voltage pre-generated.
M -M build a two cascade connection to increase the output resistance; all transistors operate in the low inversion region to reduce the power consumption. In the low-inversion region, the drain-source current is given by: If the ratio W/L of the NMOS transistor M is made Q times larger than that of M and both have the same L, V of transistor M and M can be reformulated in terms current I as  This current is independent of the power source and is much smaller, than the current operating in typical saturation region. With such a constant and small current, the voltage on the drain of transistor M can be as stable and independent of the power supply. To minimize the lowest workable RF input power for the whole transponder, such a reference is expected to work under a power supply voltage as low as possible. The zero-threshold PMOS transistors M3 -M4 are used as the current mirror load to reduce the required Vds voltage drops. A low power regulator is simply a differential amplifier with feedback. The feedback detects the output voltage and compares it with the Vref provided by the voltage reference of the second step. For the differential amplifier, an NMOS amplifier is selected with an active PMOS load. In order to achieve low drop regulation and ensure that M18 operates in the saturation region, the native MOS transistor with large W / L is used. Voltage divider used in proposed voltage regulator consists of resistances and can divide the output voltage value (vdd1) and give an output vdd2. Vdd2 is given by (22), with vdd2=1V to obtain vdd1=0.5V must be equals .

RESULTS AND ANALYSIS
The simulation results of proposed power generating circuit are introduced in this section. Figure 8 shows the transient response of vdd1 and vdd2. Vdd1 and vdd2 with different input power levels whiche changes from -22dBm to 14 dBm are shown in Figures 9 and 10 respectively. In -22dBm input power, the obtainable largest conversion efficiency is still 29.15%, which is higher than the reported results shown in comparison table. With 29.15% power conversion efficiency the communication distance of RFID system is about 10m. Table 1 introduces our work efficiency compared to other works [5], [11], [12], [13]. The layout for the power generating circuit for an UHF RFID tag circuit is shown in Figure 11. All devices or circuits prone to produce electromagnetic interference or susceptible to interference are enclosed with double layer guard rings. The layout is done by respecting following items; design rules (DRM, MRC and Density) and designer constraints information (constraint manager, text). It occupies an active area of 0.25mm2.

CONCLUSION
In conclusion, a new power generating circuit for a UHF RFID transponder with multiple output supply voltage has been successfully designed in TSMC 180 nm technology. Circuit design, simulation, analysis and layout design are all included in this study. The performance of the proposed power generating circuit is enhanced a good accuracy of the voltage supply which is stable and independent of the power voltage levels as the power supply for a UHF passive RFID tag.