Optimization of PFC cuk converter parameters design for minimization of THD and voltage ripple

Received Sep 17, 2018 Revised Nov 29, 2018 Accepted Dec 14, 2018 This paper presents the optimization of PFC Cuk converter parameter design for the minimization of THD and voltage ripple. In this study, the PFC Cuk converter is designed to operate in discontinuous conduction mode (DCM) in order to achieve almost unity power factor. The passive components, i.e., inductor and capacitor are designed based on switching frequency and resonant frequency. Nevertheless, the ranges of duty cycle for buck and boost operations are 0<D<0.5 and 0.5<D<1, respectively for the output voltage variation of the converter. The principle of the parameters design optimization is based on the balancing energy compensation between the input capacitor and output inductor for minimization of THD current. In addition, the selection of high output capacitance will minimize the output voltage ripple significantly. A 65 W PFC Cuk converter prototype is developed and experimentally tested to confirm the parameters design optimization principle. The experimental results show that the THD current is reduced to 4.5% from 61.3% and the output voltage ripple is reduced to 7 V from 18 V after parameters optimization are realized. Furthermore, it is confirmed that the output voltage ripple frequency is always double of the input line frequency, 50 Hz and the output voltage ripple is always lower than the maximum input voltage ripple.


INTRODUCTION
In recent years, portable electronic equipment has advanced from a power converter and has the advantages of high efficiency, small in size and possess a wide input and output voltage ranges [1]- [3]. On the other hand, the conventional power converter is not able to operate in a wide operation range and at the same time maintaining high efficiency; especially when the step up and step down voltage conversion need to be achieved [4]- [6]. Besides, battery voltage decreases as the battery discharges and lead to various difficulties if there is no voltage control. Therefore, the most effective method of regulating voltage through a circuit is by using a DC/DC converter. Cuk converter can be used as a DC voltage regulator due to the ability of the converter to stepping-up or stepping-down the voltage with negative polarity depending on the application requirement. In addition, the traditional telecommunications equipment requires an input power DC of -48 V [7] and contains numerous parallel-redundant rectifiers which convert the input AC power to output DC power. Besides, the telecommunications networks and information technology equipment has converged causing the power equipment need to have a various input power requirements [8]. Therefore, it is a challenge to telecommunications facilities designer to construct a reliable and economical power converter so that it ableto support various input power requirements [9]- [11]. In order to convert the available input AC source from grid to DC source -48 V, a full-bridge rectifier is required to rectify the input AC to output DC while Cuk converter is a suitable conveter to be used to convert the output positive polarity to negative polarity [12]. The Cuk converter is a modified boost-buck converter and can be used either to step up or step down the output voltage with respect to the duty cycle. The integration of these two converters which are the full-bridge rectifier and the Cuk converter namely the PFC Cuk converter. Nevertheless, the use of bridge rectifier, transformer, inductor, and capacitor can produce the DC output voltage without any distortion however will cause the input current to be extremely distorted. Hence, a rectifier i.e., AC/DC conversion is totally required in PFC converter structures to ensure the input voltage and input current are purely sinusoidal. Several circuit topologies; boost, buck-boost, Cuk, and SEPIC converter have been developed for PFC applications. However, the PFC Cuk converter has several drawbacks i.e., high THD current at the input side as well as high voltage ripple at the output side due to the output voltage from the full-bridge rectifier produced inconstant DC.
This paper presents the optimization of PFC Cuk converter parameters design for the minimization of THD and voltage ripple in order to overcome its drawbacks. Besides, to reduce the THD current at the input side, the principle of balancing energy compensation between the input capacitor, C1 and output inductor, Lo is concerned. Meanwhile, the output voltage ripple can be reduced by optimizing the output capacitance, Co. Therefore, the energy from the output full-bridge rectifier must be transferred to the Cuk converter effectively without any "extra" energy. If the energy is not effectively transferred, the input THD current is affected at the input side and increases the output voltage ripple. The parameters are designed based on the standard of IEC 61000-3-2, which is class D i.e., maximum of THD current is 5% [13]- [15]. The PWM signal for the switch is realized using Altera DE2 as in [16], [17]. The results of the optimization produced an output of -48 V with the THD current is down to 4.5% and the maximum output voltage ripple is approximately 20% of the output voltage.

CONVENTIONAL PFC CUK CONVERTER
A conventional PFC Cuk is a type of conventional PFC converter with the integration of full-bridge rectifier and Cuk converter that allows the step-up and step-down of output voltage by controlling the duty cycle. Figure 1 shows the full-bridge rectifier part that requires four standard-diode as a bridge, while large input inductance L1 and large output capacitance Co are required for the Cuk part. The operation of Cuk is the same as the conventional buck-boost converter with constant DC source, which the output voltage is always in negative polarity.
Generally, the characteristics of the conventional PFC Cuk converter and Cuk converter are different, which the Cuk converter receives a constant DC as the supply while the PFC Cuk converter receives a not constant DC source. Therefore, a large input inductance and ouput capacitance are required for the structure of PFC Cuk converter. Nevertheless, the output voltage can be stepped-up or stepped-down with appropriate components design for both structures. When the same specifications and parameters of the Cuk converter are applied in the conventional PFC Cuk converter, the THD current and output voltage ripple become high. Therefore, the inductance and capacitance of the output inductor and capacitor, respectively are required to be optimized in order to reduce the THD current and output voltage ripple.

Basic Principle of PFC cuk converter
Theoretically, when a duty cycle approaches unity, the DC gain towards zero [14]. The switching frequency need to be considered for parameters optimization purpose. When the switching frequency increases, the ripple curret on the inductor decreases. Figure 2 shows the DC gain characteristics for the PFC Cuk converter. Besides, the structure as depicted in Figure 1 consists of buck and boost operations where for the buck operation, the duty cycle is less than 0.5 and the duty cycle is greater than 0.5 for the boost operation.

Operation of PFC cuk converter
The PFC Cuk converter circuit with single-switch is controlled by duty cycle signal. This circuit can be divided into six operating modes and consist of positive and negative half cycles, referring Figure 1.
Mode-1 and Mode-4: Mode-1 is positive half cycle while mode-4 is negative half cycle. When the switch S is turned-on, the energy from source is stored in inductor L1. At the same time, capacitor C1 is discharging to inductor Lo and capacitor Co. During this interval, the diode Do is turned-off and the power supplied to the load.
Mode-2 and Mode-5: Mode-2 is positive half cycle where mode-5 is negative half cycle. When the switch S is turned-off, the inductor L1 recharges the capacitor C1, and inductor Lo recharges the capacitor Co through the freewheeling diodes Do and supplies power to the loads.
Mode-3 and Mode-6: Mode-3 is positive half cycle while mode-6 is negative half cycle. During the same state when the switch S is turned-off, the capacitor C1 and inductor Lo store energy through the discharging inductors L1. The capacitor Co are discharging. During this interval, the diode Do is turned-off and the power supplied to the loads. Table 1 shows the specifications to design the passive elements. Based on the operation mode, the passive elements are estimated based on the DCM condition.

Design of input inductor
The input inductors L1 are expressed in (1) with input voltage (VAC) is in positive and negative half cycles.

Design of output inductor
The voltage conversion ratio M in terms of the rectifier parameter can be obtained by applying the power-balance principle [13]: To ensure the operation is in DCM, the following value of Ke is selected:

Design of output inductor
The capacitor C1 will not cause low-frequency oscillations with the converter inductors. Thus, the energy transfer from capacitors C1 is determined based on the inductor L1, and Lo such that the line frequency (fL) should be lower than the switching frequency (fs). Thus, a better initial approximation for choosing the resonant frequency (fr) is given by [5]:

Selection of output capacitor
The output voltage ripple frequency of the converter is two times of the input frequency. Therefore, Co can be obtained as follows: Figure 3 shows the optimization parameters of Lo and C1 with THD current, however the allowable THD current range must be within 1.8% to 4% in order to estimate Lo and C1 for optimization purpose. Energies of Lo and C1 must be compensating each other. Otherwise, the remaining energy of Lo will be transferred to the source and consequently the quality of input current line will be affected. As has been mentioned, the THD current of 2% is used as a reference to ensure the efficiency of the proposed converter is high and THD current is low, according to the standard of IEC 61000-3-2. The output capacitor ripple current, Δic1 and capacitor voltage ripple, ΔVc1 are expressed by (10) and (11). In addition, the output voltage ripple is expressed by (13).

Optimization parameters design of PFC cuk converter
Based on (9), the output voltage ripple is reduced when capacitance increases. After all the parameters are optimized by considering availability in the market, the PFC Cuk converter specifications are listed as shown in Table 2.

RESULTS AND ANALYSIS
Referring to the Table 2, the simulation and experimental results are discussed by focusing on the minimization of THD current and output voltage ripple. To reduce the THD current, the inductance of the output inductors are set to 2.2 mH and 22 µH while the capacitance of the output capacitors are set to 470 µF and 3300 µF in order to observe the output voltage ripple reduction with the switching frequencies of 10 kHz and 50 kHz.

Minimization of THD current
During the simulation of the converter circuit, all the switching devices and components are assumed ideal with no losses. Figure 4(a) and Figure 4(b) show the input source voltage and input source current, respectively for the PFC Cuk converter. The quality of the input current is poor. This means that the THD current is very poor in this condition and the percentage of the THD current of the input line current is 61.3%. Figure 5 shows the frequency spectrum of THD current before optimization. In other words, the input line current is not a pure sinusoidal as the input line voltage because the input line current contains single harmonic distortion. The optimized parameter is needed to ensure the harmonic limits is always within the range of IEC 61000-3-2 standards. The parameters for the hardware experiment listed in Tables 1 and 2  shown in Figure 1. The THD current is measured by using power analyser and all data are tabulated in one graph. In addition, the inductance of the output inductors, Lo used are 2.2 mH and 22 µH with a fixed capacitance of the output capacitor, Co which is 3300 µF and the switching frequency is 50 kHz to observe the THD current in terms of the ripple current as shown in Figure 6. From Figure 6(a), the THD current of Lo = 2.2 mH is used and the result of the input THD current is high at the input line current with THDi of 61.3% with peak-peak current is 10 A and peak-peak voltage is 160 V. In Figure 6(b), the Lo = 22 µH is used and produces the THDi of 4.5% with peak-peak current is 7.4 A and peak-peak voltage is 160 V. In addition, the position of the sine wave is in phase. From Figure 6, when large inductance of the output inductor is considered, the THD current is poor and the output voltage ripple frequency is double from the line frequency for one cycle as shown in (14). The output DC is depending on half-wave and full-wave bridge rectifiers is shown in Figure 7. However, the output voltage ripple is decreased which will be discussed in the next section. Meanwhile, Figure 8 shows the frequency spectrum with various frequencies and output capacitor values. The harmonic components are collected from the fundamental harmonic to 11 th harmonics by using power analyser. The switching frequency of 50 kHz and the output capacitance of 470 µF produce the 3 rd and 5 th highest harmonics which results in a high THD current. However, for the 7 th and 9 th harmonics component, the current is low compared to the other harmonic components magnitude. It means that to reduce THD current with regard to standards IEC 61000-3-2 which is less than 5%, the 3 rd and 5 th should be minimized as low as possible. Figure 9 shows the frequency spectrum of THD current after optimization which is 4.5%.  Figures 10 shows the comparison of the output voltage and ripple current when the capacitance of the output capacitor used are 470 µF and 3300 µF with a fixed switching frequency of 50 kHz. It can be seen that the output voltage ripple is reduced from 18 V to 7 V when the capacitance of output capacitor is increased. Furthermore, the output current ripple also decreases from 0.60 A to 0.16 A when the capacitance is increased. Besides, the output ripple frequency of the structure is two times of the input frequency. Figure 10(a) shows the output voltage ripple with the output capacitor of 470 µF. In this case, the output voltage ripple is 18 V and the output current ripple is 0.60 A. It can be seen that the experimental results is approximately agree with the simulation results. The spike of the output voltage waveform is depending on the parasitic elements. When the output capacitance is 3300 µF, the output voltage ripple is reduced to 7 V and output current ripple becomes 0.16 A. This is because when the capacitance is high, the output voltage ripple is reduced. Thus, the function of the capacitor is to reduce the output voltage ripple as shown in Figure 10

CONCLUSION
This paper has presented the optimization of PFC Cuk converter parameters design for the minimization of the THD current ripple and the output voltage ripple. A prototype of the PFC Cuk converter with optimized parameters has been proposed and experimentally confirmed. The experimental results have shown a good agreement with the designed parameters. The THD current is 4.5% after parameters optimization. Satisfaction of IEC 61000-3-2 less than 5% requirement have been achieved by balancing the energy compensation of passive elements. Moreover, the output voltage ripple 7 V is reduced significantly with the output frequency is two times of the line frequency. Other than that, with higher power factor and efficiency, the structure can be used to most of the consumer electronic appliances. This topology uses the combination of full-bridge rectifier and Cuk converter structures with single-switch (MOSFET). A high power factor can be achieved by applying appropriate PWM switching schemes.