3.3V DC output at-16dBm sensitivity and 77% PCE rectifier for RF energy harvesting

Received Oct 25, 2018 Revised Jan 12, 2019 Accepted Mar 5, 2019 This paper presents a high voltage conversion at high sensitivity RF energy harvesting system for IoT applications. The harvesting system comprises bulk-to-source (BTMOS) differential-drive based rectifier to produce a high efficiency RF energy harvesting system. Low-pass upward impedance matching network is applied at the rectifier input to increase the sensitivity and output voltage. Dual-oxide-thickness transistors are used in the rectifier circuit to maintain the power efficiency at each stage of the rectifier. The system is designed using 0.18μm Silterra RF in deep n-well process technology and achieves 4.07V output at -16dBm sensitivity without the need of complex auxiliary control circuit and DC-DC charge-pump circuit. The system is targeted for urban environment.


INTRODUCTION
In recent years, much attention has been placed on the Internet of Things (IoT) technology. IoT refers to the vast network of physical devices that are connected to the internet via built-in sensors, software and necessary electronic circuits allowing the devices to send, receive and exchange data [1,2]. The 'Things', for example home appliances are put into home network and can be controlled by using voice, remote control or smartphone via the internet. In large-scale deployment area such as Smart Cities, billions of sensors are needed to control the 'Things'. These wireless sensor nodes are normally powered by batteries which are known for its limited lifetime and the use of batteries in large area network are not practical as it involves the cost of purchase, maintain and dispose of large amount of batteries [3]. There are also few cases where the application of batteries are not feasible such as device that is used to monitor a structure or the environment (e.g. volcano) due to the need of recharging or replacing the battery. As the alternative solution to the limitations of batteries, energy harvesting system is used to power the IoT devices.
Energy harvesting is a process of harnessing energy from ambient environment and converts the energy into electricity to power electrical or electronic devices [4]. Energy from sunlight, vibration, radio frequency (RF) [4,5] and etc. is captured, to be used directly or accumulated and stored in a storage component like a battery or a capacitor for a period of time for later use. RF energy has very less power density compared to other energy sources and can be easily integrated into a small chip making it suitable for IoT applications [6]. Furthermore, RF energy is available for almost everywhere and anytime thanks to the growing of radio wave sources such as wireless LAN transmitters (Wi-Fi) [7], TV [5,[7][8][9], FM/AM radio, mobile base stations [5,9] and mobile devices [5]. RF energy is a form of differential alternating current (AC) sources and rectifier is required to convert the differential signal captured by antenna into single direct 1399 current (DC). The output of rectifier will be passed to few circuits to form a reliable output before the output signal can be used for electronic circuits. Due to low density of the harvested RF source from ambient environment, it is important to achieve an energy harvester system with high sensitivity. This paper is organized as follows: Section 2 discusses principle of RF energy harvesting system and reviews the previous designs of rectifier for energy harvesting. Section 3 introduces the architecture and characteristic of the proposed system. Section 4 presents the simulation results and discussions of the proposed circuits followed by the conclusion in Section 5. Figure 1 shows the typical RF energy harvesting system. RF energy is captured by antenna and converted into DC voltage by rectifier. Typically, the output voltage produced by rectifier is small and decreases as the sensitivity increases due to the nature of antenna that captures very small energy [6]. Therefore, impedance matching is applied between the antenna and rectifier to provide maximum energy transfer to the circuit [10][11][12]. The sensitivity of rectifier determines the capability of a rectifier to be operated when very small energy is available in the surrounding. High sensitivity allows efficient transmission of energy at greater distances from RF sources [13]. Due to the small output voltage produced by rectifier, DC-DC charge pump is used to boosts the output voltage to a higher usable voltage level [7,14]. The voltage then is regulated by voltage regulator to provide a stable DC voltage that is independent to input voltage and load current.

RF ENERGY HARVESTING WORKING PRINCIPLE AND DESIGN REVIEW 3.1. Rectifier
The efficiency of rectifier is critical in designing RF energy harvesting system. High efficiency rectifier reduces power dissipated during the RF-DC conversion. Rectifier efficiency is defined by the power conversion efficiency (PCE) factor as in (1) where Ploss is the conduction power losses in the rectifier. The efficiency depends on threshold voltage (Vth), channel resistance (ron), leakage current and current drive capability of rectifier [6]. Low Vth, ron, leakage current and high driving capability reduce the voltage drop across the rectifier, thus increasing the efficiency. PCE, η% = P out P in = P out P out + P loss × 100 (1) Figure 1. RF energy harvesting system The low Vth and leakage current can be achieved by applying differential-drive rectifier (DDR) circuit as shown in Figure 2. DDR consists of 4 transistors with cross-connected gate structure to form a complimentary bridge rectifier. The gate of transistors is actively biased by differential mode signal at two nodes, Vx and Vy [15]. When Vx is positive, Mn2 and Mp1 are in forward bias and act as small on-resistance causing the Vth of the devices to decrease effectively [15]. The transistors will turn-on when Vx reaches the Vth. On the other hand, as Vy is negative, Mn1 and Mp2 are in reverse bias causing the Vth of the transistors to increase, reducing the reverse leakage current. The differential signal applied at both of the input of rectifier allows both low Vth and leakage current to be achieved simultaneously, increasing the efficiency and sensitivity. The output voltage produces by DDR is defined as in (2) where VRF is the input AC signal and Vdrop is the voltage loss across the transistor during circuit operation.

Design review
There are few types of rectifier architectures have been proposed for the application of RF energy harvesting. For example, Dickson multiplier or also known as voltage multiplier has been used by [16] as shown in Figure 3 to convert the RF signal into DC. In order to achieve high sensitivity rectifier, all of the transistors used in the rectifier are operated in weak inversion. One parallel inductor or a shunt inductor is applied between the antenna and the rectifier to work as voltage boosting circuit to further increase the sensitivity. The rectifier is designed with few types of transistors include zero Vth transistor (ZVT), zero Vth transistor with thick oxide (ZVTDG), low Vth transistor (LVT), normal Vth transistor (NFET) and 3.3V I/O transistor with thick oxide (NFET33) rectifiers with different numbers of stages to differentiate the effects of the Vth to the sensitivity. At -22.1dBm and 10-stages with ZVT technique, the rectifier able to produce an output voltage of 1V. -32.1dBm sensitivity is achieved at 50-stages rectifier with LVT technique and producing 1V output voltage. Although the rectifier has very high sensitivity, the output however is small and not adequate to supply electronic circuit that requires 3.3V supply voltage. It also has too many stages which consumed large area and space. Another way to increase to output voltage is by increasing the load however this might greatly decreases the efficiency considering large voltage loss experienced by the rectifier as the number of stage increases as shown by (3). Figure 3. Dickson multiplier [16] D. Karolak proposed an enhance voltage multiplier circuit by implementing bulk-biased or dynamic threshold MOSFET (DTMOS) to the rectifier to reduce the Vth of the transistor thus decreasing the voltage loss across the rectifier [17]. The rectifier is cascaded to 3-stage to increase the output voltage. At 900MHz and -2.3dBm sensitivity, the rectifier produced an output of 1.2V with 48% power efficiency. In DTMOS transistor, the bulk which usually connected to the source in conventional transistor is connected to the gate or the drain of the transistor, as shown in Figure 5. This has forcing the body-to-source voltage (Vbs) to be equal to gate-to-source voltage (Vgs). When Vgs = Vbs = 0, the Vth is high, causing the leakage current to reduce. When Vgs = Vbs = Vmax (amplitude of input signal), the source and the substrate is in forward bias forcing the Vth to drop.

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Although DTMOS transistor has low Vth, its operating voltage however is limited to its Vth [18,19]. This is due to excessive increase in leakage current when the applied voltage exceeds the Vth [18,19]. This type of rectifier also introduces large voltage drop across the rectifier as the stage of the rectifier increases. Further increasing in load resistor or stage of the rectifier to increase the output will greatly decrease the efficiency making it not suitable for high sensitivity with large output voltage rectifier.  [20]. ULP diode composes of a pair of PMOS and NMOS transistors where the gate of PMOS transistor is connected to the source of NMOS transistor and vice versa. The body of the NMOS is connected to the lowest potential node while the body of PMOS is connected to the highest potential node. The structure of the ULP diode is shown in Figure 6. As the diode is positively biased, both the NMOS and PMOS transistors are operate in forward bias with forward current similar to the conventional MOS diode. In reverse bias operation, the source terminals of both transistors are connected together and the transistors are operated in subthreshold region. As the reverse voltage increased, the current increases with the increase in drain-to-source voltage (Vds). As the cut-off of Vgs increase, the current then decreases exponentially reducing the leakage current and maintaining a good forward current. At 900MHz operating frequency, the proposed 3-stage Dickson multiplier with ULP diode produces 0.214V output at -10dBm sensitivity with 17.74% efficiency. Another improvement on voltage multiplier performance has been made [21]. 5-stage voltage multiplier that operates at 900MHz and 50Ω input source are used in the reseach work. The output of the rectifier is connected to a voltage regulator to generate a constant DC output voltage. DTMOS-type transistor is used in the rectifier to reduce the Vth. A shunt inductor and a series inductor as shown in Figure 7 are connected between the antenna and the rectifier to increase the sensitivity of the circuit. The rectifier produces an output voltage between 1.8V to 2V at -18dBm with 18.08% efficiency. A voltage limiter is applied between the rectifier and the voltage regulator to avoid the transistors in the regulator from breaking down. As the rectifier starts to operate, the output voltage of the rectifier increases slowly until it achieved the desired output voltage. The output voltage is then regulated by the proposed voltage regulator. Very low efficiency is expected to be achieved by this rectifier to generate the 3.3V DC voltage due to the large voltage drop across the rectifier during circuit operation.  Figure 8 shows the DDR schematic [22]. The rectifier is cascaded to 5-stage and operates at 915MHz. An off-chip series inductor is applied at the rectifier's input to resonate the capacitance from the rectifier and boosts the quality factor (Q-factor) in order to achieve high efficiency rectifier. At -3dBm sensitivity, the rectifier achieves 66% power efficiency and produces 4V DC output voltage. In comparison with the previous rectifier discussed in this section, this proposed rectifier produces better efficiency and high output voltage. The output voltage is adequate to power low-power electronic devices. The sensitivity however is low, and the circuit will not be able to operate when very little RF signal is available in the surrounding. Increasing the load resistor able to increase the sensitivity however this costs the power efficiency. The rectifier is designed using standard 0.35µm process technology. High output voltage generated by this rectifier might damaging the device because the output has exceeded the transistor's breakdown voltage [22]. A. K. Moghaddam proposed a double rail differential-drive rectifier with an enhance DTMOS body biasing technique as shown in Figure 9 and Figure 10  1403 efficiency at 5.2dBm sensitivity and 2kΩ load resistance. A maximum of 3.5V output voltage is produced at this sensitivity and efficiency. Although the rectifier has good power efficiency and able to generates 3.5V output voltage, the sensitivity however is too low. In order to obtain higher output voltage at higher sensitivity, larger load resistor is required. However, further increasing in load resistance reduces the efficiency. Furthermore, DTMOS transistor has lower Vth and leakage current thus providing better efficiency when compared to the conventional bulk-to-source transistor. However, this ability is limited by the transistor's Vth as DTMOS transistor's body current increases excessively when Vgs exceeds the Vth [18,19]. Generating large DC voltage at higher sensitivity will greatly decrease the rectifier's efficiency.

PROPOSED RF ENERGY HARVESTING SYSTEM 3.1. Dual-gate-thickness differential-drive rectifier
Due to the ability of differential-drive based rectifier providing both low Vth and leakage current simultaneously, the proposed rectifier is designed by implementing bulk-to-souce (BTMOS) differentialdrive based rectifier cascaded in to 6-stage to achieve high DC output voltage at high sensitivity. Typically, the rectifier is designed by using thin-oxide transistor as it has small channel length, ron and fast switching speed which are very important in achieving high efficiency rectifier. However, the physical ability and structure of this transistor is limited by the voltage operation such that its gate and drain voltage are limited to 1.8V only [24]. Further increasing in operating voltage applied to this transistor may cause to poor transistors' performance and breakdown.
For high voltage operation, thick-oxide transistor should be used. Thick-oxide transistors have much thicker gate-oxide-layer and longer channel length allowing it to operate at much higher voltage than the thin-oxide (between 3.3V to 5V) [22]. It has lower speed performance when compared to the thin oxide but has lower leakage current which is beneficial in maintaining the efficiency of the rectifier.
The proposed rectifier is divided into two parts as shown in Figure 11. The first three stages are designed by using the thin-oxide transistors and the next three stages are designed by using thick-oxide transistors. Both types of transistors are used in this proposed circuit to achieve better efficiency at each stage of the rectifier since thin-oxide and thick-oxide transistors have the best performance at lower voltage and higher voltage operation respectively.

Low-pass upward matching network
In ideal case where the system is lossless, maximum voltage is transferred from the source to the rectifier, resulting high sensitivity system. Practically, the impedance of the source and rectifier impedance is not the same and voltage losses are presented in the circuit [25]. If source resistance is higher than the main circuit, most power ends up being reflected at the source. To force the rectifier impedance to be equal as the source, low-pass upward matching network is used to deliver a pumped-up voltage from the source to the rectifier. The circuit is said to achieve maximum power transfer when the rectifier impedance is equals to the source resistance (RS) as shown in (4) where ZS is the source impedance and ZR* is the complex conjugate of the rectifier. R_RECT and jX_RECT is the rectifier resistance and reactance respectively.
Low-pass upward matching network shifts upward the impedance of R_RECT to be identical as the RS. Figure 12(a) shows the modelling diagram of DDR and its resistance and reactance with a low-pass upward L-matching network. Since the rectifier mainly composes of transistors, its reactance typically consists of capacitance which carries the negative reactance (C_RECT) [25]. To eliminate this negative reactance, a positive reactance is needed. This is shown in Figure 12(b). The inductor, L_RECT* which has positive reactance, will resonate the negative reactance of the C_ RECT leaving only the identical source and rectifier resistances. The matching circuit consists of parallel capacitance (XP) and series inductance (XS) and sees terminations with only RS and load resistor (RL) present. The quality factor (Q-factor), XS and XP can be calculated as in (5), (6) and (7) respectively. As shown in Figure 12(b), XS is in series with L_RECT*. 1405 Therefore, the total positive reactance, XS_Total is calculated as in (8) where fS is the source frequency, CP is the capacitor in parallel, LS is the inductor in series and XL_RECT is the inductance of L_RECT*.
X S = Q factor R _RECT = 2πf S L S X S_Total = X S + X L_RECT ( 8 )

RESULTS AND ANALYSIS
The circuit is designed using 0.18µm Silterra RF CMOS in deep n-well technology. The system is designed to match a 50Ω source impedance at 900MHz input frequency that is capable to produce at least 3.3V DC voltage at minimum of -15dBm sensitivity. RF deep n-well transistor type is used in the rectifier circuit to isolate the substrate of the NMOS from its origin substrate to form a bulk-source transistor.

Proposed rectifier
The performances of the proposed rectifier circuit are shown in Figure 13 and 14 for schematic and post-layout simulation respectively. The rectifier achieves the highest PCE of 78.76% with 3.904V output voltage for pre-layout simulation and 77.07% of PCE with 4.067V output voltage for post-layout simulation at -16dBm sensitivity.

Impedance matching
In impedance matching network, reflection coefficient (Γ) or also known as S11 determines how much power is reflected from the antenna or the source. Reflection coefficient is the ratio of the signal reflected from the load to the incident signal and can be calculated as in (9) where ZL and ZS are the load and source impedances respectively. The higher the reflection coefficient, the better the match between the source to the termination circuit. The voltage standing wave ratio (VSWR) is a measure of how well a transmission line is matched to the load. VSWR can be calculated as in (10) [26]. As discussed in Section 3.2, low-pass upward impedance matching network as shown in Figure 15(a) is applied at the input of rectifier to transfer maximum input power from the source to the rectifier. From Figure 15(a), the total input impedance (Zin) is defined as Zin  XL + XC and XL  L and XC = 1/C. L and C are the inductor and capacitor values and  is the angular frequency. Rewriting the equation, Zin can be defined as in (11) and the matching network can be reconfigured as shown in Figure 15(b). It should be noted that (11) is the general equation to represent the input impedance. The real reactance depends on the transistors models and sizing and is calculated through S-parameter (SP) analysis in Cadence. From the schematic simulation, the total input impedance of the rectifier without the matching network is equals to 27.99 -j1624. By applying the equation from (5) until (8) and (11), the total ideal inductor and capacitor values would be around 145.8nH and 3.15pF respectively. With the matching circuit, the rectifier achieves the 50Ω source resistance with very small reactance and obtained high reflection coefficient value as shown in Figure 16. Ideal inductor and capacitor are electronic components where no parasitic elements are considered. In practice, parasitic elements exist in these components and the total inductor and capacitor values might be different from the ideal components. In IC design industry, inductor contained very high parasitic capacitance due to its physical structure that usually is formed from the top metal elements. Thus, a fine tune of inductor and capacitor should be done to match the rectifier impedance with the source resistance. In this proposed circuit, the matching network is realized on-chip and the capacitor and inductor are built from MIM capacitor and asymmetrical square inductor (with optimized Qfactor). The post-layout proposed rectifier achieved the highest S11 when the on-chip inductor and capacitor values are at 40.827nH and 1.0555pF respectively and the impedance, Z11 and S11 are shown in Figure 17. The layout of the proposed rectifier and on-chip matching network has a total core area of 1486.1µm x 1178.1µm as shown in Figure 18. Table 1 Figure 16. Z11 and S11 Pre-layout DDR with impedance matching Figure 17. Z11 and S11 Post-layout DDR with on-chip impedance matching Figure 18. Proposed DDR and impedance matching core layout

CONCLUSION
An energy harvesting system that is capable to generate at least 3.3V output voltage at very high sensitivity has been proposed. The system consists of 6-stage BTMOS DDR and low-pass upward impedance matching circuit to obtain high sensitivity and output voltage rectifier. In order to obtain high efficiency rectifier, dual-oxide-thickness transistors are applied to the rectifier. The rectifier is divided into 2 parts where the first three stages of the rectifier are designed by using thin-oxide transistors for stage's output voltage lower than or equals to 1.8V and the next three stages are designed by using thick-oxide transistors for stage's output voltage higher than 1.8V. This is to avoid the rectifier in thin-oxide from performing poorly after it reaches the maximum 1.8V operating voltage and if using thick-oxide transistor for the whole 6-stage rectifier, it will reduce the PCE as smaller channel length is needed to increase the PCE of rectifier. The proposed rectifier produces 4.067V output at -16dBm sensitivity with 2.39µA load current. Due to the high voltage produced by the rectifier, the need of DC-DC charge pump to boosts the output voltage of rectifier that is typically used in conventional RF energy harvesting system is eliminated which saves the size of core area and the cost of fabrication. The system is targeted for urban environment where the RF sources are easily accessible.