Nine-level inverter with lesser number of power semiconductor switches using dSPACE

Received Jul 24, 2019 Revised Jan 20, 2022 Accepted Jan 27, 2022 In this paper, a single-phase nine-level multilevel inverter (MLI) topology is created in which reduced number of switches, diodes and gate driver circuits can be used so as to obtain higher output voltage levels. Due to this configuration, the blocking voltage value across the switches will also get reduced. In this proposed single-phase MLI topology, increase in output voltage levels can be observed whenever there is increment in the number of switches in the configuration. Proper mathematical modeling and analysis of the voltage waveform of the proposed inverter have been done for a 9-level MLI. MATLAB platform is used for modeling and simulation of the MLI. Modulation index is varied in order to observe various outcomes through simulation. The proposed nine-level inverter configuration is experimentally evaluated in the laboratory for various modulation indices so as to validate the simulation results. Comparison of this topology is done with the classical MLIs in order to illustrate its advantages.


INTRODUCTION
It has been 35 years since the introduction of multilevel inverters (MLIs) [1] and still this area of study fascinates researchers and industrialists all around the world. MLI produces a higher output voltage levels in comparison with conventional 2-level inverters. These higher output voltage level waveforms have inherently lesser harmonic content, lesser switching losses, high voltage compatibility, enhanced power quality with better electromagnetic compatibility. MLIs are used in motor drives, reactive power support, and renewable energy sources (RES) [2]- [4]. The main objective of MLI is to obtain the desired AC waveform using several DC sources and power electronic switches [5], [6].
Numerous topologies of MLIs have been created including the classical topologies of neutral point clamped (NPC) MLI [7], [8]. Flying capacitor (FC) MLI [9], [10] and cascaded H-bridge (CHB) MLI [11], [12]. Unequal sharing of voltage among the capacitors connected in series and requirement of clamping diodes are the problems associated with NPC MLI. The storage capacitors are subjected to unbalance voltages and also the bulky circuits are the demerits in FC MLI configuration. CHB MLIs require the least number of power electronic components (IGBT, capacitors, and diodes) among the classical topologies [13]- [15]. But they require separate H-bridge for each of the DC sources [16], [17].
A new type of MLI with reduced no of semiconductor power switches has been proposed [18]. This MLI topology requires additional number of bidirectional semiconductor power switches. Also, the magnitude of blocking voltage is higher across these bidirectional semiconductor power switches. Some MLIs with reduced switches, single isolated DC source having other DC sources replaced with capacitors and control techniques are presented [19]. Single DC source CHB (SDC-CHB) with control algorithms such as one-  [20]. The MLI topologies using the half bridge and T-type converter has been proposed [21]. Various modulation techniques are available in literature for the modulation of MLI [22]. Among them, the high-frequency pulse width modulation (PWM) technique such as level-shifted PWM and carrier phaseshifted PWM technique [23], [24], space vector modulation techniques (SVM) have been used [25]. Furthermore, synchronous optimal PWM [26], [27], active harmonic elimination [28], selective harmonic elimination [29], and nearest level control [30] methods are described as low semi-conductor switchingfrequency modulation technique.
In this article, a novel topology of symmetrical MLI with lesser number of power electronic switches in comparison with classical topology, is presented. The proposed inverter optimizes the inverter for attainment of various objectives like minimization of IGBTs, power diodes, and gate drivers resulting in reduced cost, higher efficiency and simple control techniques. The proposed 9-level MLI structure is simulated in MATLAB platform and then the output results have been validated experimentally in the hardware set up for both resistive and inductive loads at various modulation indexes. Figure 1 represents the proposed topology of the MLI. It uses ten power electronic switches (Sa, Sb, SL1, SL2, SL3, SL4, SR1, SR2, SR3, and SR4) and four isolated DC voltage sources (VL1, VL2, and VR1, VR2). Four identical dc sources, VL1, VL2, VR1, and VR2, are used to provide DC voltage to the proposed MLI. The inverter generates 9-levels if the ratios of the input isolated DC voltages (VL1: VL2: VR1: VR2) is chosen as 1: 1: 1: 1.  Table 1 represents the switching sequence of the proposed MLI. Here, 1 and 0 respectively represent the ON and OFF states of the switches. The various modes of operation of this MLI are clearly represented in Figure 2. specified. It can be observed in Figures 2 (a) and 2 (b) that a zero level can be obtained by switching ON the upper switches SL1, SR1, and Sa or the lower switches SL2, SR2, and Sb. We will get the positive voltage level VL1 by turning ON the switches SL3, SL1, SR2 and Sb as shown in Figure 2 (c). The figure represents only the positive current flow through the load but it works for negative current flow as well. To get a level having double the value of DC voltage used, we turn ON the switches SL4, SL1, SR2 and Sb which is shown in Figure 2 (d). In Figure 2 (e), we can observe another level getting added up as another DC source comes in the picture when we turn ON the switches SL4, SL1, SR1, SR3, and Sb. Another level is achieved by turning ON switches SL4, SL1, SR1, SR4, and Sb which gives us four times the value of DC voltage which is represented in Figure 2 (f). This completes our positive half cycle of the output which is shown in Figures 2 (b) to 2 (f). Using the same mechanism, the negative half cycle can be generated which is shown from the Figures 2 (g) to 2 (j).

Generation of output voltage levels
The voltage levels in output (Nlevel), no. of IGBTs (NIGBT) and maximum output voltage (Eo,max) is given by: Here 'm' is the total number of dc voltage sources.

Modulation & control technique for the proposed MLI
For generation of gate pulses for the switches, various methods like the fundamental switching frequency method, sinusoidal PWM (SPWM) method, space vector PWM method, can be implemented. Here, we are using SPWM technique is implemented for generation of the pulses for the switches of the proposed inverter. PD-PWM (phase disposition PWM), a level shifted PWM technique is used here. In this technique, a sinusoidal reference waveform at the fundamental frequency is compared with eight triangular carrier signals of very high frequency to generate the PWM switching signal for the proposed 9-level MLI. These eight signals are Vcr4-, Vcr3-, Vcr2-, Vcr1-, Vcr1+, Vcr2+, Vcr3+, and Vcr4+ as represented in Figure 3. The pulses obtained through this method are combined with appropriate digital logic gates to obtain the gate pulses are shown in Figure 4.  The output voltage waveform along with the FFT analysis for different modulation indexes (MI) is shown in Figure 5. The simulated results of the inverter voltage and the FFT analysis corresponding to the nine-level can be seen here. The variation in fundamental component of the output voltage and total harmonic distortion (THD) can be observed with the change in M.I. As shown in Figure 5 (a), the output voltage obtained is 79.77 V with THD 11.10% by keeping the value of M.I.=1. If we change the value of M.I. to 0.7, output voltage obtained is 55.47 V with THD 17.82% as shown in Figure 5 (b). Further decreasing the value of M.I. to 0.3, output voltage obtained is 39.24 V with THD 22.20% as per Figure 5 (c).

CONCLUSION
In this article, a novel 9-level symmetrical MLI topology with lesser number of power electronic devices, in comparison with classical MLI topologies, is proposed. The proposed inverter optimizes the inverter for attainment of various objectives like minimization of IGBTs, power diodes, and gate driver circuits resulting in reduced cost, higher efficiency and simple control techniques. The simulation of MLI is performed in MATLAB software. The results of simulation are then verified with the experimental results obtained in the laboratory through the hardware set up for resistive and inductive loads with different values of modulation indexes.