Using sigma-delta quantizer based PI for inductive power transfer systems

In this paper, a Sigma-Delta Quantizer (Σ4-Q) based Proportional and Integral control is proposed for a wireless power transfer control system, namely inductive power transfer system. The proposed control topology employs Σ4-Qs to convert the conventional signals (analog/digital signals) into bitsreatm signals (1-bit per sample time). Considering the oversampling feature of Σ4-Q, field programmable gate array is utilized in the implementation of the control system. To evaluate the effectiveness of the presented control topology, it is compared with an inductive power transfer control system using the conventional proportional and integral controller. For the sake of simplicity, the comparison is carried out using hardware in Loop. Both control systems exhibit almost identical responses. However, the bitstream feature of the proposed PI controller significantly helps in reducing the hardware resources (logic elements) in field programmable gate array. In addition, less wire routing and computational complexity is achieved due to absence of multipliers.

INTRODUCTION Due to the large consumption of fossil fuel in the world, many countries have actively involved in the usage of renewable energy for sustainability and the pollution reduction. The weakness of using renewable energy, especially solar energy, is that it is intermittent and variable [1]. This intermittent nature requires conventional power plants or massive storage facilities such as battery banks as reservations. With the developments of electric vehicle (EV), a novel technology so-called vehicle to grid (V2G) system attract the attention of both academia and the industries [2,3]. With V2G technology, the energy can be stored in the EVs' battery. The huge amount of car batteries could be integrated to a battery bank for power grid. In order to achieve the V2G system, the EVs have to plug in and out very often and convenient. Dragging charging cables everywhere is not an appropriate solution. With the recent development of power electronics technologies, a fascinating wireless power transfer system, so-called bidirectional inductive power transfer (BIPT) system is shown to be ideally suited for the V2G systems. Generally speaking, BIPT can be operated automatically and effectively used in as a wireless charger and discharger system. In the literature, it is recommended to make BIPT systems operate at a range of frequency between 10 and 40 kHz in order increase the efficiency of the Ì ISSN: 2088-8694 entire system [4][5][6][7][8]. Further, the performance of the BIPT system could be enhanced by combining it with compensations. However, the BIPTs together with the compensations inevitably become more complicated with high-order resonant networks; and thus a robust controller with simple topology is required. Typical discrete controllers, designed for power electronics, are often implemented on field programmable gate array (FPGA) due to the high speed and parallel processing FPGAs offer [9,10]. Thus, all the interfacing signals with BIPT including the signals in the processors have to be converted to digital signals with 8-bit, 16-bit, or 32-bit signed fixed-point representation. Mixed-signals integrated circuits such as analog/digital, referred to as A/D and digital/analog, referred to as D/A converters are important to be used the proposed BIPT control system. Most A/D converters consists of uniform multi-level static quantizer which in turn require multi-wires to transfer data. Transmission of multi-bit word could be disordered when the transmission becomes sophisticated. Furthermore, general arithmetic operation including summation or multiplication, are processed simultaneously (parallel computing), which results in high routing consumption in FPGAs and complicated signal processing. One widely dynamic A/D converters equipped, so-called Sigma-Delta modulation (Σ -Q) has attracted the mixed-signal circuits designers due to its feature in the reduction of the data transmissions, routing, wiring and signal processing [11,12]. One of the main advantages of using Σ -Q is that it converts the input signals to single-bit signals (1-bit per sampling time) which provides unique features over in any digital signal processors [13,14].
In the signal processing field, using Σ -Q offers many important advantages including the nature of its output signals which is represented by single-bit (boolean logic signals). Representing signals by bitstream signals (one-bit by sampling time) highly reduce the data-transmission and routing to single wire per each single-bit signal. Secondly, single-bit signals are inherently digital signals and therefore, signal conversion from single-bit signals to their equivalent digital signals to interface with digital signal processor is not needed any more. Thirdly, the single-bit signal processing are not only simpler than conventional Nyquist rate processor but also consumes less energy and hardware resources (logic gates) [15][16][17]. In the control filed, several papers [18,19] showed that the Σ -Q can effectively be employed to control power drivers directly as a replacement of PWM, which is often the case in many applications such as DC-DC converters and DC-AC inverters. Recent researches combing conventional PID and generalized proportional integrals (GPI) controllers driven by singlebit signals have been studied in [20][21][22][23], respectively. The stability of such control systems has been analyzed using sliding mode theory, and such system has been made feasible in controlling the DC motor.
In this paper, motivated by the above features of using single-bit signal processing, a proposed PI that interface with single-bit signal i.e., using single-bit signal processing technique, is programmed on so called field programmable gate array (generally abbreviated as FPGA) to control a the power flow in typical BIPT system. The single-bit feature of the proposed PI controller helps in reducing the hardware resources (logic elements) in FPGA. In addition, less wire routing and computational complexity is achieved due to absence of multipliers. The paper is presented as follows: Section II introduce the dynamic of typical BIPT system and its control problem. Section III show how the simple system of Σ -Q to derive single-bit PI. In the result section, simulation and experimental results of the closed-loop BIPT system are presented shoing the advantages of using Σ -Q in the hardware reduction with some conclusions presented in the final part of the paper, Section V.

TYPICAL BIPT SUBSYSTEMS
The topology of a typical BIPT is a well-established system and shown in Figure 1. As can be seen, the BIPT allows the the power to flow with no physical contacts from the primary subsystem to secondary subsystem and vice versa. The secondary subsystem of the shown BIPT is connected through H-bridge. When the power flows wirelessly through the air-gap from primary subsystem to pickup subsystem, then primary subsystem acts as an inverter whereas pickup-subsystem acts as a reversible rectifier. Similarly, the primary subsystem behaves as the reversible rectifier and the pickup subsystem operates on inverting mode when the power wirelessly transfers from the pickup subsystem to the primary subsystem. The objective of the primary subsystem converter mainly is to generate a constant track current with high-frequency in windings of the the primary subsystem L pt whereas the main goal of of the pickup converter is to manage and direct the power transmission between both subsystems. Note that both sides of the system , i.e., primary and pickup subsystem comprise inductor-capacitor-inductor LCL resonant networks to track the current generated by the the converter employed in the primary subsystem. Furthermore, the parallel compensation for the BIPT essentially acts as the energy source with efficiency reach up to 94% [5]. S1+ S2+ S1-S2-S1+ S2+ S1-S2-

Primary Secondary
Primary Controller Secondary Controller

Operation
The BIPT system illustrated in Figure 1 is to be simplified further using the equivalent circuit in Figure 2. In the equivalent circuit, it is often considered that the primary subsysetm is connected with an AC voltage source to generate sinusoidal voltage V pi ∠0 with ω frequency . Similarly, the pickup converter is considered to be connected with an AC voltage source with a phase angle θ w.r.t the AC voltage source connected with the primary subsystem, which is denoted as V si ∠0. The maximum power transmission between the primary subsystem and secondary subsystem can only be achieved when the phase difference θ equals π/2, see [24] for more details. In the normal operation, the LCL circuit is tuned to the track frequency ω, such that L pi = L pt and L si = L st . Therefore Under these assumptions, the simplified system shown in Figure 2 can be represented by what is called the π model, see Figure 3. The shown π model can be utilized to mainly determine and accordingly control and the track current I pt in primary subsystem and the input current I si in the the pickup subsystem. Both currents are expressed as: in which M denotes the mutual inductance between the the track coils inductance L pt and pickup inductance L st , given by where k denotes coefficient of the coupling in the BIPT considered in this paper. It is also known that the converter in the pickup subsystem generates power expressed by From (5), it implies that the power transmission can can be effectively optimized by controlling the phase angle θ and the output voltage V si . For example, the maximum power can be obtained if the phase θ equals ±90 • . This means that the pickup subsystem is functioning at power factor (PF) equals 1. For BIPT systems, when θ equals 90 • , then the power is transferring from the pickup subsystem to primary subsystem, and if θ equals −90 • , then the BIPT opertaes in the reverse mode, i.e., power is transferring from the primary subsystem to the pickup subsystem, See [5] for more details. Thus, the output power in (5) is optimised by directed by controlling the phase difference between the primary subsystem and the secondary subsystem in which with D denotes the duty cycle of D = α p /π = α s /π. Consider (6) and (7), by substitute both equations into (5), the output power from the primary susbsystem to the pickup subsystem can be measured by the following equation: in which α p denotes the phase shift between the two converter on/off signals connected to the H-bridge in primary subsystem. Similarly, α s denotes the phase shift between the two converter on/off signals connected to H-bridge in the pickup subsystem. Consider both (5) and (8), controlling converter in the pickup subsystem and accordingly output voltage V si is to be used to regulate (control) the lead/lag phase difference between on/off signals that used to switch two legs of the converter. Therefore, the main objective of the proposed controllers in BIPT is to effectively control the phase difference between the on/off signals to optimally control of the power transmission between the two subsystems.

Control algorithm for BIPT
The control algorithms for the considered BIPT systems can be designed to control the duty cycle to control switch of the H-bridge [4,24,25] and the phase control [5,3]. The controllers for both control problems are mainly known by 1) the controller connected to the primary subsystem and 2) the controller connected to a feedback pickup subsystem. loop primary control subsystem and the same switch signals are used to the same H-bridge connected to the pickup subsystem controller but without a feedback loop [24]. This section illustrates the control design for duty cycle of the pickup subsystem controller. The problem of designing controller for the duty cycle basically starts from considering (8). Thus, the control laws can be obtained by effectively controlling the phase shift α s between two switches S 1 and S 2 of the converters in pickup subsystem. Indeed, changing the duty cycle of the switching signals connected to the converter directly changes output voltage and accordingly control the power transferring from the primary subsystem to the pickup subsystem in return. The phase delay θ between the primary subsystem and pickup subsystem is fixed at either ±90 • based on the desired direction of the power transferring. The controller for primary subsystem should be designed to control the phase shift α p in order to sustain a constant sinusoidal track current. However, to reduce the distortion of the harmonics at the minimum, the phase shift is fixed to α p = 120 • . Figure 4 illustrates controller schematic designed for the duty cycle. Since we used a FPGA for our controller design, the all the input signals must be converted to digital signals. Therefore, we used A/D to convert the continuous-time input voltage and current connected to the pickup subsystem to digital signal. Next, both digital signals (voltage and current) are multiplied by each other to get the power value. The measured input power will be compared by the reference signal (desired) and the results (error) will be by the controller to generate control signal. A phase locked loop (PLL) is effectively designed as a clock that generated by FPGA and utilized for system synchronization by measuring the phase of the output voltage of the primary subsystem. The phase shift α s between the two switches S 1 and S 2 of the converter connected to the pickup subsystem changes between ±180 • , in which 180 • gives in the optimal power transfer in forward direction; and −180 • gives in the optimal power transfer in the other direction.

SINGLE-BIT BASED CONTROLLER
Single-bit based control design, which uses Σ -Q significantly contributes in the reduction of the routing area and hardware resources (logic elements consumption) since there is no multiplier needed to design the controller. This section presents the concept of single-bit signals generated by Σ -Q, and the design of single-bit based proportional and integral controller for BIPT system.

Single-bit signal and Σ -Q
The single-bit signal is switching signal which represented by ON or OFF quanta denoted by +Q and −Q. It could also represents any bipolar time domain signal. The single-bit signals are generated by various types of two-level quantizers including Σ -Q, which converts its input signals to switching signals (called here single-bit) signal. Figure 5 illustrates a typical first order Σ -Q. The dark line shows the input signal to be converted to single bit signals ( dotted line). As can be seen, the output of the quantizer is expressed by The quantizer sensitivity is represented here by Q. [15]. See the BIPT system in Figure 1. As mentioned earlier, the steady state error is the difference between the measured power and the desired power, i.e., e = P ref − P sdc in which P ref and P sdc denote the desired and measured power of the pickup subsystem, respectively. The get an optimal performance and guarantee stability of both Σ -Q and BIPT system, the quantizer gain Q should be carefully set larger than input signals to be converted, in our case e. The condition can be written as |e| ≤ Q . However, the value of Q should selected as close to the maximum value of e as much possible as we can to avoid unnecessary quantization noise during quantisation process [21]. Optimally, Q should be set just equal the maximum boundary of e.

Single-bit based controller
The controller schematic driven by single-bit can be designed using either single-bit blocks with input/output single-bit signals or recently hybrid PI controller [15]. Employing several single-bit blocks to execute any mathematical operations requires many Σ -Qs (double number of the blocks) and thus, requires very careful deign process in selecting the proper Q values used in each block. As any quantizer, Σ -Qs introduce quantization noise and therefore, the proportional and the integral using single-bit blocks have to be carefully designed in order to minimize the quantization noise. For this reason, the hybrid single-bit PI, which is proposed to control BIPT system, is given bŷ where k p and k i denote the proportional and integral gains, respectively. The controller driven single-bit based is often designed using input-output interface in boolean logic (on-off) format. In other words, a Σ -Q is designed to convert the input signals to single-bit signal which in turn , will be applied to the digital processor to execute the control law, see [15,17] for more details. In this paper, PI controller embedded with Σ -Q is implemented on FPGA. Firs, we convert the continuous-time system into its discrete-time approximation using Euler's discretization method. The discrete-time transformation of (10) shown in Figure 6, is expressed bŷ with ρ = z − 1 and K U i = QT s k i , K Li = −QT s k i , T s denote the sampling period. The dark line is the conventional signal whereas the thin line represents the single-bits signal, see [15]. Figure 6. Hybrid single-bit PI

SIMULATION AND EXPERIMENTAL RESULTS
To investigate the performance of the proposed controller driven by single-bit, the controller is designed and used to effectivley control the power transferring in a BIPT system . The validation and verification are carried out though simulations and experiment. Since the PI control strategy had a good performance in simulations, the single-bit controller would use PI format, too. The system parameters of bidirectional IPT system is given in Table 1.

Simulation
The main objective of this work is to replace the conventional PI by the a PI controller driven by single-bit signals. For BIPT, the designed controller will be used mainly to control duty cycle which will result in modifying the phase difference between converter switches. Thus, the single-bit signal should switch with constant frequency. Since Σ -Q generates single-bit signals with variable frequencies, then these signals can be used to drive the BIPT converters. Therefore, Σ -Q is replaced with conventional PWM for this purpose. As can be seen in Figure 6, the control signal is conventional signal to be converted through PWM in order derive H-bridge switches. Figure 7 compares the performances of PI controller drive by single-bit signals and the conventional PI controller. Both controllers were used to control and direct the power transferring in both forward and reverse modes. It is very clear that PI controller with the single-bit signal interface can be used as a replacement for the conventional PI controller for the power flow between the BIPT subsystem. It is also evident that there is oscillations in the transferred power when the BIPT is operated at steady-state. At high power rating, the oscillations is acceptable in single-bit PI in comparison with conventional PI controller. However, it is noted that as the magnitude of the power transferred between the primary and backup subsystem becomes less, the amplitude of oscillations increases. The oscillations are obviously caused by the quantization noise generated by Σ -Q. In this experiment, the quantizer gain Q was set to 1210 which is obviously, large enough Q to introduce more noise to the system at lower power ratings. To partially mitigate the high oscillation and improve the performance, simulations with variable Q numbers (fine Q settings) were carried out in the literature, see [26]. In this work, the PI controller is programmed using DE0-nano FPGA. Table 2 shows FPGA hardware consumption for both; the conventional PI controller and the PI controller embedded with Σ -Q. The consumption of hardware resources by the PI controller embedded with Σ -Q are 586 LEs and 154 dedicated Logic Registers (LRs). IHowever, the conventional PI controller consumes 1302 LEs, 182 dedicated LEs and 24 9-bit multipliers. It is evident that the single-bit based PI controller dramatically reduces hardware resources, routing and no multipliers needed by the processor.

CONCLUSION
In this paper, a new PI schematic with Σ -Q has been designed and tested on a prototype BIPT system. The usefulness of this PI has been verified in both simulation and HIL environment. With a proper design, the proposed controller achieve a good performances in comparison with conventional PI controller. The single-bit signals representation and multiplier-less schematic significantly simplified the design of the controller on hardware level. The compilation reports generated by FPGA software has showed a dramatic reduction in hardware resources that consumed by PI controller embedded with Σ -Q.