Implementation of SVM for five-level cascaded H-bridge multilevel inverters utilizing FPGA

Received Sep 3, 2019 Revised Dec 20, 2019 Accepted Feb 16, 2020 The Space Vector Modulation SVM technique has won large acceptance for AC drive applications. However the utilization of multilevel inverters connected with SVM by Digital signal processor (DSP) raise the intricacy of control algorithm or computational load, increases of the obtaining distortions output voltage. The development of SVM in multilevel inverters may offer higher numbers of switching vectors for acquiring further enhancements of output voltage performances and implement by using Field Programmer Gate Array (FPGA), investigate lower Total Hormonic Distortion (THD). This paper reports the performance evaluation of SVM for five-level of Cascaded H-Bridge Multilevel Inverter CHMI using MATLAB/Simulink, which is sampled at the minimum sampling time, i.e. DT = 5 μs. The switching signals for driving insulated gate bipolar transistor (IGBTs) which are stored in MATLAB workspaces, are then used to be programmed in FPGA using a Quartus II software. Which can be stated the lower THD of the simulation result is about 14.48% for five-level CHMI and experiment result is about 14.31% for five-level CHMI at modulation index M_i=0.9. The error percentage between the simulation results and experimental results of the fundamental output voltage in SVM is small which is approximately less than 1 %.


INTRODUCTION
Many AC drive applications utilize Voltage Source Inverters (VSI) which have evolved as the most popular power conversion. The involvement of VSI is in line with the development of various Pulse Width Modulation (PWM) algorithms supported by the advent of solid-state switching device technologies, fast digital signal processors, Field Programmable Gate Arrays (FPGA) in order to create a PWM signal for the real-time and microcontroller system as means of a digital processing. Since a few decades ago, several PWM algorithms have been developed to improve some performances of VSI such as high-power efficiency [1][2][3][4][5]. Few studies indicated that they are not accounted for PWM control with high frequency and diversified techniques of sampling, produce greater output voltage with optimum fundamental value, keep total harmonic distortion (THD) lower within the critical range with lower ratio of switching frequency to fundamental frequency [6]. Apparently, the research about VSI, thus far, has not reached to the state of saturation, as novel or simplified PWM methods are still emerging for various topology inverter circuits and multilevel inverters [7]. Through various types of modulation strategies or PWM methods, a Space Vector Modulation (SVM) technique has gained wide acceptance because of several advantages such as higher output voltages, lower THD, high-efficiency and flexibility to be implemented in vector control systems [8]- [13]. Besides that, this modulation scheme also offers in optimizing the used of dc voltage link utilization which means it can increase the ration of output magnitude voltage. In general, the implementation of SVM involve with the used of DSP board and required sector identification which brings into the formations of rotating space vector diagram. In the three phases system, there are six fractions in the space vector diagram spinning 360° which each has equally divided by 60°. This space vector diagram is a transformation from a balance of three phase quantities into two phase system of α-β reference frame. The SVM main operation is to use the nearest three vector recognition of the reference voltage and determined the corresponding on-time using the principles of volt second equivalent [14][15][16][17].
A multilevel inverter offers greater number of voltage vectors as compared to eight vectors for a two-level inverter. Figure 1 illustrates the space vector diagrams for Sector I, in a two-level inverter and three-level inverter. The space vector diagrams can be used to compare the implementation of SVM in twolevel and three-level inverters. As compared to two-level space vector diagram, the sector in three-level inverter is divided into four identical smaller triangles (i.e. ∆_0, ∆_1, ∆_2 and ∆_3). To reduce THD (or dv⁄dt) and switching losses in multilevel inverter (i.e. three-level), it is necessary to switching vectors which are the nearest to the reference vector v ̅ _s^*. Hence, three-level SVM switch the vectors v ̅ _2, v ̅ _7 and v ̅ _14for a given reference vector. The calculation of on-duration in multilevel SVM is quite complicated and different for various triangles due to small triangles in the space vector diagram of three-level inverter in Fig.1 do not exactly imitate the geometry of a sector of two-level inverter. In two-level SVM, the calculation of on-duration is straightforward which is valid for every sector. However, the three-level SVM needs to modify the reference vector with new origin point to apply the two-level based SVM for calculating onduration. As shown by Figure 1 (b), the modified reference vector v ̅ _s^* with vector v ̅ _2 as origin point is determined such that the calculation of on-duration is like that of two-level based SVM. The calculation becomes complicated if the reference voltage vector v ̅ _s^* lies in triangle ∆_2, where the orientation of triangle is different among others; as can be seen the triangles ∆_0, ∆_1 and ∆_3 have the same orientation with a single triangle or Sector I in two-level SVM, as shown in Fig.1. The complexity increases as number of levels of inverter becomes higher, e.g. in five-level inverter, there are six triangles among sixteen triangles, that have different orientation The implementation of SVM for multilevel inverters require some important parts which are as follows; (1) detection of sector , (9) detection of triangle ∆ , (10) calculation of on-duration for switching the nearest vectors, and (11) determination the switching sequence for every switching period. As found in literature, there are two common methods to calculate the on-durations. The first method is to detect the triangle and solve three simultaneous equations of the triangle to determine the on-times as suggested in [18]. The second method is to detect the triangle and use on-duration equations stored in a lookup table for this triangle, as proposed in [19,20]. Both methods however require complex computations as the number of level increases. Alternatively, the calculation of on-duration can be obtained using general algorithms. Specifically, uses a Euclidean vector system with several matrix transformation, provided that it does not provide a systematic approach for real time SVM implementation. On the other way, calculated on-duration and obtained switching states by means of coordinate system, where the axes are 60 degrees apart. However, the 60 degrees transformation leads to the complexity since the voltage reference is commonly defined in the orthogonal coordinate system. Recently, a simple SVM algorithm for multilevel inverters based on standard two-level SVM. The two-level based SVM concept is initiated by [21], however, the calculation of on-duration is based on origin modification and 60 degrees coordinate transformation, which cannot be extended in implementing SVM for higher levels, i.e. L greater than three. Unlike the former methods, the implementation of SVM that includes the detection of sector and triangle, and calculation of on-duration were derived geometrically and systematically which suitable for any level of inverter [22-24].

RESEARCH METHOD
Based on the investigation in literature review about type of PWM, the SVM is preferable as it offers several advantages and recently known as the most popular technique for many electrical drive applications. This chapter discusses the development of space vector modulation (SVM) algorithm based on five-level cascaded H-bridge multilevel inverters as proposed by [18,25]. It is necessary to describe the principle or formulation of the SVM algorithm with the aid of suitable diagrams and equations for every level of inverter is given to develop a proper modulator for evaluating its performances THD. The performances evaluation will be presented in results and discussion. Then, the simulation model of SVM for every level of inverter is developed using MATLAB-Simulink. The development of the simulation model uses same parameters values, e.g. sampling time, three-phase load, DC voltage, etc., as implemented in the hardware system. The verification and evaluation are also carried out via experimental. In the hardware system, the SVM algorithm is executed using a Field Programmable Gate Arrays (FPGA) DEO Controller. The implementation of the hardware system emphasizes on some important aspects for proper SVM operations, providing a blanking time generator to avoid short circuit conditions, ensuring the DC voltage supply for each H-Bridge inverter circuit has provides isolation and a constant DC voltage and applying gate driver circuits which have sufficient power amplifications and isolation to switch ON/OFF the IGBTs of VSI. Once the simulation and experimental results are obtained, all the recorded data is tabulated in tables, and graphs for comparison to performance evaluation. Then, based on suitable equations and theories, the analysis of performances is carried out to verify the improvements/advantages of using different type of levels of inverters which is five-level cascaded H-Bridge multilevel inverters. The development of hardware is used to obtain the experimental results which will be compared with the simulation results, validation of SVM algorithm as well as the advantages of SVM in multilevel inverters.

Space vector modulation of five-level cascaded H-bridge multilevel inverter
This section briefly describes the principle of SVM for five-level CHMI based on two-level SVM. Since the SVM control algorithm is based on two-level SVM, it can be proven that most parts utilize same equations and approaches for implementing the switching modulations. Figure 2 depicts a five-level Cascaded H-Bridge Multilevel Inverter (CHMI) which consists of six isolated DC voltages. The CHMI shown in Figure 2 is referred to five-level inverter is due to the fact that the inverter can produce five levels of output voltages, which are 2 5 , 5 , 0, − 5 and −2 5 . The five output voltages can be obtained by providing possible switching state combinations on the simplified circuit of the five-level CHMI (i.e. for a single-phase) given in Figure 2. Hence a single-phase output voltage of the CHMI (i.e. -phase where = -, -, or -phase) can be expressed as: = ( 1 − 2 ). 5 + ( 3 − 4 ). 5 (1) The triangle for five-level CHMI as shown in Figure 4 is defined using (2) and (3). It can be shown that each sector will have 16 triangles (i.e. ∆ 0 , ∆ 1 , ∆ 2 ,…, ∆ 15 ).
The discussion above shows the different parts utilized in five-level CHMI as compared to that of three-level, where the five-level CHMI involves greater numbers of triangles, level output voltages and voltage vectors. The rest parts will utilize same approaches and equations. For example, the on durations for switching vectors in five-level CHMI are calculated using (4), (5) and (6).

Simulation model of space vector modulation
This section presents a simulation model of Space Vector Modulation (SVM) using MATLAB-Simulink. Figure 5 depicts the simulation model, specifically the control algorithm of SVM which generates switching status. The simulation model shown in this figure is used to generate switching states for driving IGBTs of five-level CHMI by modifying the number of inputs and DC voltage terms in some calculations. The simulation is performed using two sets of sampling times, such as 1 = 200 for detecting sectors, triangles and computing on-duration, and 2 = 5 for generating appropriate pulse width with highlinearity and accuracy. Generally, the simulation model is constructed using two types of programming approaches, namely the graphical programming approach using Simulink blocks and the c-programming approach written in MATLAB function blocks. There are two inputs required in the simulation model which are the demands of magnitude and frequency. These two inputs will produce a reference of three-phase voltage. The Simulink blocks inside the Subsystem1 for generating the reference of three-phase are presented in Figure 6. It can be seen that the reference is constructed using (7). * = .
(2 ) (5) * = . ( where is the magnitude of reference voltage. By considering the limitation of the possible output voltage produced in the SVM for five-level CHMI, the magnitude can be calculated as follows: = Μ where Μ can be varied between 0 to 1 for adjusting the magnitude of input and hence output voltages. This means, Μ is set to 1 for producing the maximum output voltage. The three-phase voltage is then transformed into reference voltage components * and * , as the input of the modulator. The transformation is obtained using (9) Using these equations, the transformation is constructed using Simulink blocks as presented in Figure 7. These Simulink blocks are grouped as a Subsystem2, as shown in Figure 5. It can be noticed from the complete simulation model shown in Figure 5 that the reference voltage components * and * are sampled at 1 = 200 using Zero-Order Hold blocks. These two inputs are used to produce reference voltage vector into a polar form using (11) and (12). Then, the magnitude and angle of reference voltage vector, i.e. * and are being fed to MATLAB Function1 block for detecting sectors , triangles Δ , and calculating * and * , as discussed in previous sections. The source code or cprogramming written in the MATLAB Function1 block as shown in Figure 8. * = √ ̅ * 2 + ̅ * 2 (11) The reference voltage components * and * produced from MATLAB Function1 block are then used as the inputs of MATLAB Function2 block. This block is responsible to calculate on-duration for switching vectors within a triangle for five-level CHMI. The source code for calculating on-duration shown in Figure 9. The on durations and produced from the MATLAB Function2 block are used to calculate duty ratios of pre-switching states for each phase, , and . The calculation is performed by Subsystem3 block, as can be noticed in Figure 5. Figure 10 shows Simulink blocks contained in Subsystem3 block, which are constructed using (13), (14) and (15)  At the last part of Figure 5, it can be observed that all the information such as sector ( ), triangle (∆ ) and pre-switching states ( , and ) for selecting appropriate switching states to drive IGBTs of five-level CHMI. That performed by MATLAB Function3 block, as shown in Figure 5, the source code as shown in Figure 12 is given first sector ( ) at first triangle (∆ ). Finally, the switching states are used to drive IGBTs of the inverter. Figure 2 depicts simulation models for five-level CHMI. Note that, the switching of IGBTs is determined by the switching states, provided that the switching of upper and lower IGBTs for each leg must be complimented to each other. The output of each inverter is connected to an identical three-phase and series connected resistive and inductive loads.

The description of experimental setup
In this section describes the assignments of the circuits or components employed to set up the experimental platform for verifying the effectiveness of SVM technique for five-level cascaded H-bridge multilevel inverters. The structure of experimental platform indicated the components used, as shown in Figure 13. The Field Programmable Gate Arrays (FPGA) Controller was utilized to perform the tasks of SVM technique. The Field Programmable Gate Arrays (FPGA) Controller is known to have high-speed clock which is superior to execute logical or digital operation. It featured a powerful Altera Cyclone IV EP422F17C6N FPGA with 22,320 logic elements, 32 MB of SDRAM, 2 kb EEPROM, and a 64 Mb serial configuration memory device. The FPGA board 40-pin Headers (GPIOs) provided 72 I/O pins, 5V power pins, two 3.3V power pins and four ground pins, 153 maximum FPGA I/O pins and 56 embedded multipliers. The DE0-Nano board included a built-in USB Blaster for FPGA programming, and the board could be powered either from this USB port or an external power source. Inputs and outputs included 2 pushbuttons, 8 user LEDs and a set of 4 dipswitches. The board included expansion headers to attach various terasic daughter cards or other devices. Figure 13 shows the FPGA receives information of Quartus II program and pre-switching states , and

FPGA controller
. The FPGA is accountable to perform the assignment of selecting suitable switching states based on the date received. This task is similar to the MATLAB Function3 block as depicted in Figure 5.

Quartus II program for FPGA controller board
The Quartus II absorbed the data obtained from the switching signals for driving IGBTs stored in MATLAB workspaces. Then, the data were saved in Excel file. Next, the data were transferred to mif file. The first part in programming created a project name (New Project), family and device settings for FPGA. The number of word (4001) were selected which could transfer the data from 12 switching states of Excel file to 12 switching states of mif.file. This file consisted of 0-4000, then, displayed the mif file. at Quartus II. The Mega Wizard Plug-In Manager would insert (sa1…sa4, sb1…sb4 and sc1…sc4) under (mif file). VHDL file was created and saved as 'svm5level'.vhd for computational purposes. In addition, other VHDL Files saved as 'clk_div'.vhd, 'blanking_comparator'.vhd, 'blanking_lower_counter'.vhd, 'blanking_mod18'.vhd, 'blanking_upper_counter'.vhd and 'blankingteme_main'.vhd, edit coding were created as shown in Figure  13. Then, the project was analysed after verifying the success of the analyses. The assigning pin on FPGA selected pin planner for 2 inputs and 24 output pins 12 lower switching outputs and upper switching outputs. Hence, a full compilation design was successful to programme the FPGA hardware in order to see the display of output waveform on oscilloscope, as shown in Figure 14.  Figure 15 the FPGA for circuit cascaded H-bridge multilevel inverter CHMI and gate driver e.g. for five-level. The FPGA controller, it applied the date from Quartus II Program to absorb the gate driver and power inverter circuits they are used to produce desired output voltages. The aim of use gate driver circuits was to provide isolation between the electronic control circuits and power inverter circuits and provide enough power expansion for switching IGBTs. Hence, the same switching states were produced from the output of gate driver circuits, yet, with different grounding points. The identical switching states were used to drive IGBTs in CHMI with enough voltage and current. Figure 15 showed the six units of H-Bridge inverter circuits to plant five-level CHMI as shown in Figure 2. Every H-Bridge inverter circuit was supplied by an isolated DC voltage supply.  Figure 16 in which simulation results as well as experimental results are shown at figures, it can be observed that the experimental results are in close agreements with the simulation results. The compered obtained between the fundamental output voltage in SVM technique being enhanced about 15% of that obtained in the conventional SPWM technique at same modulation indices = 0.9 as shown in Figure 17. Note the results are obtained using sampling time 2 = 5

Power inverter and gate driver circuits
i.e. at fast rate of computation, where the error between the simulation and experimental results is insignificant and approximately less than 1 %.

CONCLUSION
This paper has provided in-depth verified the advantage of multilevel inverter CHBI producing lower total harmonic distortion THD output voltage for five-level inverter, via simulation and experimental results. It has shown that the experimental results are nearly to the simulation results of the SVM technique, thus verify the effectiveness and proper operation of the SVM hardware implementation. The similarity between the simulation and experimental results as well as similarities between the fundamental output