A new multilevel DC-AC converter topology with reduced switch using multicarrier sinusoidal pulse width modulation

Received Sep 9, 2019 Revised Nov 8, 2019 Accepted Jan 3, 2020 Multilevel converters have a significant role in power processing control in the power system, which has some inherent features like reduced harmonics, high power & medium voltage, reduced voltage stress. In this proposed paper, a novel multilevel inverter with reduced number of switches and without passive components. The proposed inverter generates 15 level output voltage with suitable switching pulse generation using multicarrier sinusoidal pulse width modulation (MSPWM) and different level of voltages are obtained with variation of modulation index. Also coupled inductor is used to minimize the harmonic content and smoothing output current. The scheme which includes different range of unequal voltage sources. As a result, the proposed system it reduces switching control complexity and there is no voltage balancing problem. This paper elucidates the operating modes, voltage stress minimisation and harmonic reduction are discussed. The results of the proposed multilevel dc-ac converter are verified using matlab/simulink. The simulation & hardware results of the proposed inverter were verified using matlab simulink and dsPIC controller respectively, which was analysed with different voltage level and different modulation index.


INTRODUCTION
As a outcome of high technologies growth, the power requirement and quality of power are better than earlier. Because of evolution in power semiconductor devices and power conversion methods [1]. The scheme which is used to transfer DC source to AC source is called inverter. The level of the inverter increases to stabilise the voltage and reduces ripple content [2]. Generally multilevel inverters are used for high power medium voltage applications, by connecting series of power switches with lower voltage dc sources to generate staircase output voltage. Multilevel inverter acts as intermediate device, which transmit power to electrical units like grid system, UPS, FACTS devices, electrical drives and others [3].
Among various multilevel inverter topologies like neutral point clamped, capacitor clamped and cascaded H-bridge, which are mostly prepared standard topologies [4,5]. The unequal voltage balancing in the DC link capacitors lead to increase of clamping diodes as the voltage level increases, which is limitation of neutral clamped inverter [6]. And in flying capacitor inverter, capacitors act as clamping diodes and it become more complex due number of capacitor and total harmonic distortion increase based on level of inverter. In cascaded H-bridge inverter, the utilisation number of dc source increases, due to that voltage balancing problem, unequal switching, voltage stress and redundancy phase voltage increases [7]. To reduce the THD of the above conventional multilevel inverters, either switching frequency of the system. But the system outcome leads to increase switching devices, conduction loss and minimise reliability of the system [8].
To overcome the above-mentioned limitations, the research moved towards to generate multilevel output voltage with reduced number of switches. The major objective of work is to increase the voltage level with a smaller number of power semiconductor switches [9]. In multilevel inverter, the ratio of output voltage levels and required power switches is termed as SLR (switch level ratio), which is used to design the minimum switched MLI. The SLR decides the number of switches used, cost of the system and output voltage levels [10]. Cost of system depends, the usage number of switches and passive elements like inductor & large capacitors [11,12].
Numerous modulation strategies were developed to control converter power switches. In that, the converter with high frequency PWM methods like carrier-based modulation, trapezoidal method, sinusoidal PWM, space vector modulation and multicarrier based PWM used [13][14][15]. Moreover, selective & active harmonic elimination nearest vector control method and synchronous optimal PWM are used for converter with low frequency PWM techniques [16,17]. Reduced switches MLIs are predominantly used nearest state control and multicarrier based SPWM schemes [18][19][20].
In this proposed work, system generates 15 level output voltage with reduced number switches. It provides better features compare conventional schemes like minimised THD, low voltage stress, controlled output current and reduces cost of the system. Power semiconductor switches used in this proposed system is controlled by multicarrier based sinusoidal pulse width modulation, which avoids the shoot through problem. In that section-2 deals about modes of operation of proposed scheme, section-3 explains about multicarrier SPWM method and section-4 discuss simulation results. Figure 1 shows the proposed novel topology for 15 levels inverter. It consists of three dc source voltages are 10V, 20V & 40V. The MOSFET power switches S1, S2, S3, S4, S5 & S6 connected directly to dc sources, which decide the level output voltage from the proposed scheme. Then switches S7, S8, S9 & S10 performing a VSI bridge circuit, which decides the positive and negative range of output voltage levels with R load is connected across bridge network. The proposed system generates 15 level output voltage with suitable gate pulse generation. Number switches used in this proposed method decided by SLR ratio, which contains totally 10 power switches. Doesn't need of any additional converter like boost converter or any resonant converter to boost voltage or to balance the voltage.

Modes of Operation
The proposed system generates 15 level output voltages (+Vdc, +6/7 Vdc, +5/7 Vdc, +4/7 Vdc, +3/7 Vdc, +2/7 Vdc, +1/7 Vdc, 0, -1/7 Vdc, -2/7 Vdc, -3/7 Vdc, -4/7 Vdc, -5/7 Vdc, -6/7 Vdc, -Vdc) are explained as follows, 1) To obtain output voltage of V0 = +1/7 Vdc, switches S2, S3 & S5 kept ON to get 1/7 th voltage from the power circuit and switches S7 & S10 are turned ON to get positive level. Figure 2(a) shows the current flow path for this mode and Table 1 shows various switching combinations for 15 level output voltage. 2) To acquire output voltage of V0 = +2/7 Vdc, switches S1, S4 & S5 kept ON to find 2/7 th voltage from the power circuit and from bridge circuit switches S7 & S10 are turned ON to get positive level. Figure 2(b) shows the current flow path for this mode. 3) To attain output voltage of V0 = +3/7 Vdc, switches S2, S4 & S5 kept ON to get 3/7 th voltage from the power circuit and from bridge circuit switches S7 & S10 are turned ON to get positive level. Figure  2(c) shows the current flow path for this mode. 4) To achieve output voltage of V0 = +4/7 Vdc, switches S1, S3 & S6 kept ON to get 4/7 th voltage from the power circuit and from bridge circuit switches S7 & S10 are turned ON to get positive output level. Figure 2(d) shows the current flow path for this mode. 5) To accomplish output voltage of V0 = +5/7 Vdc, switches S2, S3 & S6 kept ON to get 5/7 th voltage from the power circuit and from bridge circuit switches S7 & S10 are turned ON to get positive output level. Figure 2(e) shows the current flow path for this mode. 6) To realize output voltage of V0 = +6/7 Vdc, switches S1, S4 & S6 kept ON to get 6/7 th voltage from the power circuit and from bridge circuit switches S7 & S10 are turned ON to get positive output level.   Generally, voltage balancing problems arises due to non-uniform switching, non-ideal dc link capacitors, unequal commutation of semiconductor devices, unsymmetrical current and injection of current flow. It effects on performance of inverter degrades, increase of voltage stress, additional harmonic distortion and increase in load current magnitude. But this proposed system avoids above mention limitations, due to that voltage balancing not required.

Topology comparison
The proposed system compared with classic topologies like diode clamped, flying capacitor and cascaded H-bridge inverter. Among that proposed scheme requires minimum number of power switches and doesn't need of any passive elements. Table 2 shows equipments comparison of various topologies for 15 levels inverter.

MULTICARRIER SINUSOIDAL PULSE WIDTH MODULATION
To amalgamate the multilevel AC output voltage with different levels of dc input, the semiconductor power switches must switched to ON and OFF state in such that desired fundamentional is achieved with minimum harmonic distortion [21][22][23]. There are several approaches are available to select a PWM strategy for multilevel inverters like based on low/high frequency, number of switches used and voltage stress [24][25][26][27]. For classical multilevel topologies to get better performance mostly prepared space vector modulation the among various modulation techniques. But SVM is not possible when minimum number of switches used, because it cannot generate simultaneous switching pulses for multiple number of switches.
This proposed scheme implementated using Multicarrier Sinusoidal Pulse Width Modulation (MSPWM). A sinusoidal (reference) waveform is compared with numerous triangular (carrier) waveforms are scattered using phase disposition method. The peak to peak amplitude of triangular signal is Vtag, and peak to peak amplitude of sine signal is Vsin. Then the modulation index Mi is defined as, Then the output voltage of proposed system based on the applied input voltage and modulation index, which is defined as,   Figure 12. The output current is controlled with help of coupled inductor with 4.2 A is exposed in Figure 13. In classical multilevel inverter topologies, number of switches connected in a leg will increase when the level increase. Due to increase in switches of a leg, this increases possibility for shoot through condition and complexity in switching pulse generation. But this proposed system doesn't have number of switches connected in series of a leg, which avoids the shoot through condition and easy to engender switching pulses.

CONCLUSION
This paper established a novel 15 level dc-ac converter with reduced switches. Based on the SLR ratio the number of switches and level of inverter can be achieved. Proposed inverter power switches controlled by MSPWM method, and with help of coupled inductor which offer high consistency output voltage and low leakage current problem. At the same time, reducing of capacitor balancing, minimize the harmonic content and getaway from the shoot-through problem. The proposed 15-level inverter can accomplish higher efficiency, low system cost and higher reliability.
The proposed system generates 15 level output voltage with help of 10 power switches with Mi=0.99 and different level of output voltages are obtained with variation of Mi.
Accomplished better current control and voltage control of 15-level proposed inverter scheme with THD of 6.36% & 10.38% respectively.