An enhanced 17-level hybridized multilevel inverter with stair case modulation

Received Dec 11, 2019 Revised Apr 4, 2020 Accepted Jul 10, 2020 This paper proposes a hybridized symmetric cascaded multilevel inverter for voltage levels ranging from 5 levels to 17 levels. The proposed Multi Level Inverter (MLI) topology is built using a modified H-bridge inverter that results in an increased output voltage levels with a smaller number of solidstate switches. This technique enhances the h-bridge configuration from three level to five level by means of a bi-directional switch at source. Gating pulses of hybridized symmetric MLI are generated through staircase modulation. The operation and performance of the proposed topology is tested for different output voltage levels, simulation results prove that the proposed technique results in less THD at all levels with lesser power consumption and are easily applicable for renewable energy applications.


INTRODUCTION
Multilevel inverter topologies are emerged to be a versatile alternative in the area of high power and medium-voltage control. Multilevel inverters (MLI) comprise of quite a lot of input sources, capacitors, active switches, power diodes and drivers to generate the required output voltage using a suitable switching patteren [1] with an apt power quality. MLI has gain more attention because of their advantageous features like high output power quality, amplitude of fundamental component, efficiency, less harmonic distortion, switching losses, and low dv/dt. These features motivated to shift from the traditional two-level converter to multilevel converters. MLI's generates the stepped voltage waveform at the output by integrating dc source connected with its input terminals. With increasing the number of dc links at input higher and higher levels of voltages are obtained at output. Based on distinct topologies used in MLI design the dc power supplies at input can be isolated or inter-connected [2][3][4][5][6]. Because of high power outputs MLI's are mostly used in industrial applications [7]. Conventional structures such as Diode Clamped or Neutral Point Clamp (NPC) [4] and Flying Capacitor (FC) [8] used in the design of MLI's suffer from high number of diodes and capacitors in higher power applications. It is established in literatute that cascaded MLI structure is compact reliable structure in deriving high voltage and power levels [9][10][11][12][13]. Cascaded MLI's are constructed by linking number of H-bridge inverters in series [14,15] in symmetrical or asymmetrical structure. In the symmetric configuration, the magnitude of input DC sources are equal, in contrast, asymmetric MLI have different magnitude input DC sources due to which the number of output levels are more compared to symmetrical configuration with reduced Total Harmonic Distortion (THD) [16][17][18][19][20][21][22]. It is evident from the literature that  [24,25]. Although Cascaded MLI's are simpler in construction and easy to control they use higher number of switching components and dc sources. The advancements in MLI's also resulted in distinct modulation techniques. Modulation techinques are selected depnding upon converter topology and its domain of application that has its own merits and demerits. Further high or low frequency switching based modulation tecniqueis proposed [26] for MLI's with switching frequency up to 1 kHz for high power applications. One of the frequently adopted modulation techniques for MLI's is sinusoidal PWM widely used in two different forms, with the first being level shifted PWM which is widely used to generate high quality output wave form and other Phase shifted PWM techniques [14]. In second techniques, carriers are either triangular, saw-tooth or constant DC magnitude waveforms etc., and the reference waveforms are sinusoidal, sinusoidal injected with third harmonic and trapezoidal voltage waveforms. [27][28][29][30][31][32].
In this paper, a symmetric Hybridized MLI topology proposed to overcome some of the drawbacks of conventional cascaded MLI's. The proposed hybridized MLI topology adopts staircase modulation technique that generates more output voltage levels with less numbers of switches or active devices. Results obtained are validated by comparing with existing conventional cascaded H bridge MLI's.
Section II, discusses the proposed structure and possible states. A discussion on control method, losses and reliability is presented in section III. Simulation results and Comparative study are brought in section IV. Finally, the conclusion of this paper is given in section V. Figure 1 presents the topology of the novel hybridized H-bridge cascaded MLI. It comprises of five bidirectional active switches from voltage prospect (S 1 , S 2 , S 3 , S 4 and S A ) and two symmetrical input dc voltage sources. Table 1 and Table 2 shows the output levels of generated voltage using the distinct switching patterns in the proposed topology. In Tables, green cell indicates conducting device (On position) and red cell indicates non conducting device (Off position). The proposed single-phase, 5-level cascade MLI, shown in Figure 1, is a hybridized 5-level inverter. Table 1, depicts the switching pattern for a five-level output voltage generated with two positive, two negative and one zero at the output. The 5-level hybrid inverter comprises a single-phase conventional H-bridge cell, and a bidirectional switch connected to the two dc sources at center tap.

PROPOSED TOPOLOGY
In symmetrical configuration with 2 input dc sources, output level can be obtained as follows Where p is equal to the number of cells.
The number of switches is given as Similarly, a seventeen-level cascade MLI is obtained by using 4 hybridized H bridge cells. Figure 2. shows the proposed single-phase, 17-level cascaded MLI and its switching pattern are represented in Table 2. S9 S10 S11 S12 S13 S14 S15 S16 SA SB SC SD V0   Table 3. supports the developed topology as the main motto behind the developing present topology is to reduce the number of solid-state devices. The proposed topology uses only 4 H-bridge MLI's in generating 17-Level output which effectively reduced the solid-state devices by 37.5% in comparison to conventional cascaded H bridge MLI. As the number of components are reduced when compared with conventional topologies that also results in reduced switching losses and number of GATE drivers. It also has reduced circuit complexity with increased modularity and is more economic.

CONTROL METHODS
In convention and Hybridized cascaded MLI topologies one of the prominent techniques used to achieve required switching pattern is multi carrier sinusoidal PWM. As the output levels increases it require high switching frequency resulting in more switching losses. The staircase PWM applied in the present work is a mixture of sinusoidal PWM and selective harmonic elimination. Stait case PWM is derived from a sinusoidal PWM by replacing the sine wave with a stair case. Number of steps in stair case are determined based on the specific harmonic cancellation. The desired output voltage level and quality is ibtained with a proper selection of frequency ratio and number of steps in the stair case. Whenever the value of modulating signal is more than the carrier signal pulses are generated. Compared with the carrier-based PWM technique, the staircase modulation features lower switching losses since the entire power semiconductor devices operate at the fundamental frequency. Staircase modulation is proven to a feasible solution in reducing the switching losses with a low frequency. In digital implementation of stair case PWM the switching angles are determined in prior for all the 4 hybridized MLI's and are stored in a table. In this work a modulating wave has been separated in to 15 zones with each zone referring a switching pattern to obtain the voltage level in the output wave form. Figure  4. Shows the switching patterns of the power semiconductor modules of proposed topology and steppedvoltage waveform.
The staircase reference is compared with triangular carriers with different frequencies which generate the Boolean output. A logic operation is applied accordingly to get the switching pattern of the proposed MLI topology from generated Boolean output, which generates pulses for corresponding power modules is shown in Figure 3.

Calculation of switching frequency
Switching frequency for any level is predetermined using

Identification of step angle
Where k = number of step angles, z = Maximum number of steps and y = Coefficient for adjusting switching angle.
The modulation index can be obtained using Where 1 = Fundamental volatge =D.C Bus voltage.

Losses
In the operation of solid state components based circuits, conduction loss, switching loss, Off-state losses and gate losses are considered for the analysis. In general, the Off-state and Gate losses are negligible in comparison with the other two hence are neglected in the analysis.

3.3.1.Conduction losses
The conduction losses are generated in each device during ON state. In MLI's conduction losses also depends on conduction time of the device. Hence to consider the time conduction losses are multiplied by a correction factor P CON . In general, the conduction loss in MLI's is given as Where V CE is the collector-emitter voltage drop and I C is the collector current during ON-state of the device and T is the total time period, and t L-i is the total ON state time of the device in p th level.

3.3.2.Switching loss
The switching loss in the IGBT are in general given as Switching loss also depends on the switching time. In the design of MLI's calculation of switching time depends on switching frequency which becomes complex with higher frequencies. Switching loss with switching time are given as Where D sw is factor accounted for switching time =

SIMULATION AND RESULTS
In order to support the proposed cascaded MLI topology, simulations studies are carried in MATLAB SIMULINK environment with the constructed Simulink model. With the switching schemes described in Section 3, 5-level and 17-level MLI's are considered for the analysis. In a 17 Level hybridized MLI stair case PWM switching patterns T1-T4 are generated with switching frequency of 100Hz, 300Hz, 700Hz and 1500Hz against a Stair case reference wave at fundamental frequency of 50 Hz, as depicted in Figure 5 and Figure 6.

Calculation of switching frequency
Switching frequency for any level is predetermined using ℎ = * 2(2 − 1) Table 4 shows the switching frequency adopted in this paper for different output levels of the hybridized cascaded MLI.    Figure 8. shows the simulated waveforms of output voltage and load current with a R load for the 17-level inverter by selecting modulation index as 0.9 and a input source voltage Vs = 55V for each cell. It is observed from Figure. 8 that generated output voltage wave from is much closure to sinusoidal from than the convention CHB MLI's. The steady state testing has been performed with resistive load (unity power factor load) with 220 V peak to peak output voltages. The obtained output current is about 20A, peak to peak. The RMS value of the output voltage and current obtained are 155.56Vand current 14.14A respectively.
(a) (b) Figure 9. FFT spectrum of hybridized MLI and CHB MLI Figure 9 shows the THD spectrum of the proposed hybridized multilevel inverter. Form the Figure 9 (a) total THD is reduced than that of Figure 9 (b) due to the variation in the number of solid state switches in generating the same output levels. Table 5 shows the comparison between proposed hybridized MLI and cascaded H bridge MLI. The percentage level of THD are low with the proposed topology for distinct level of voltage generation. From the table it is also evident that the proposed topology results in an improved output voltage in comparison to cascaded H Bridge MLI. Comparison between both the topologies are presented in Figure 10.

CONCLUSION
A Hybridized MLI with stair case modulation scheme was proposed in this paper. It generates closure sinusoidal voltage at the output with a smaller number of solid-state switches. Two kinds of MLI's generating different output levels are tested by simulation. As the output levels increases the proposed topology considerably reduces switching devices when compared to the CHB MLI. Considerable advantages of the proposed topology are 1) As the number of levels are increased it generates output waveform closer to sinusoidal. 2) Few switching devices compared with the conventional MLI 3) Low THD 4) Low switching devices loss as device conduction time is reduced. Based on the above merits, the proposed Hybridised MLI with stair case modulation shows a better performance in comparison to convention MLI's