Performance evaluation of GaN and Si based driver circuits for a SiC MOSFET power switch

Silicon carbide (SiC), new power switches (PSW) require new driver circuits which can take advantage of their new capabilities. In this paper a novel Gallium Nitride (GaN) based gate driver is proposed as a solution to control SiC power switches. The proposed driver is implemented and is performance compared with its silicon (Si) counterparts on a hard switching environment. A thorough evaluation of the energy involved in the switching process is presented showing that the GaN based circuit exhibits similar output losses but reduces the control power needed to operate at a specified frequency.


INTRODUCTION
Power electronics technology has always evolved toward higher efficiency, higher power density and more integrated systems [1], [2]. Currently most converters are designed to be embedded into the application housing and therefore its volume is restricted by the size of the product case. This size reduction is achieved using smaller passive elements and higher switching frequencies [3], which poses new challenges system efficiency due to switching and drive losses [4].
Increasing the power density of the system without affecting the overall efficiency requires a performance improvement in the power switches. Unfortunately, silicon (Si) based power devices characteristics are reaching their theoretical limits, and exhibit important limitations regarding blocking voltage capability, operation temperature and switching frequency restricting the use of them [1], [5].
In the past years, a new generation of power devices based on wide bandgap (WBG) semiconductor materials [6] became available as commercial-of-the-shelf (COTS) products. WBG semiconductors, like silicon carbide (SiC) and gallium nitride (GaN), show improved material characteristics making them an excellent option as Si power devices replacements. WBG materials are characterized by their high electrical field strength which allows very thin drift layers with high doping rates [7], [8]. Consequently, devices based on these materials are benefited by reduced on-state resistance leading to reduced conduction losses [9]. Furthermore, carrier mobility in WGB materials is superior than in Si, allowing faster turn-on / off switching times and hence, lowering switching losses. Power devices based on WBG materials are attractive because of their low input capacitance, low conduction and low switching losses, high operation temperature and high thermal conductivity [10]. The use of these new devices allows increasing the efficiency and a considerable improvement in size and robustness of power converters. In addition to this, SiC is a preferred semiconductor compared to GaN for high-voltage and high-power device applications when both electrical an thermal limitations are considered [11].
Even though power MOSFETs based on SiC have the benefit of being a Normally Off device, their oxide layer creates a large input capacitance [12] which is a challenging problem while designing the driver circuit. This capacitance has to be charged and discharged fast enough to ensure the correct operation of the device. The driver circuit is a critical asset to exploit the superior characteristics on this type of power switch (PSW). Using a driver with insufficient current capability to control the voltage of the gate capacitance will increase switching losses prohibitively, causing the destruction of the device by overheating. The maximum operating frequency of a PSW is bounded by the current handling capacity and the internal losses in the active components of the gate driver circuit. To enable high frequency operation it is critical to reduce them to a minimum [13] while ensuring appropriate drive strength.
Low voltage high electron mobility transistors (HEMTs) based on GaN are good candidates to implement the output stage of a driver circuit. This transistors outperform their Si counterparts in every electrical aspect reducing to a minimum the capacitive load to the controller circuit without compromising the voltage handling or the thermal management of the solution itself. Potential approaches on how to drive SiC MOS-FETs have been widely evaluated by [14]- [18], but finally, all of them, implement the drivers using traditional Si based devices. On the other hand, Nagaoka et al. [12] introduces for the first time the use of a driver output stage based on GaN HEMTs utilizing discrete custom devices. In addition to Nagaoka's work, Okuda et al. [19] show the proof of concept of the GaN HEMT as part of a gate driver that targets a SiC MOSFET in a hard switching environment. Even though Okuda's work proposes the use of COTS devices, the PSW is used at low blocking voltage and drain current. Therefore, no conclusive evaluation has been published regarding the benefits of the use of GaN based devices as active devices in the gate driver circuit.
This work presents the implementation of a PSW gate driver using low voltage GaN HEMTs to control a 1200V SiC MOSFETs plus an in-depth performance evaluation and comparison against equivalent gate drivers using Si based MOSFETs and Bipolar transistors. The rest of the paper is organized as follows: section 2 introduces the concept of the driver topology and the circuit implementation details. Section 3 present the test bench setup used in the Dual Pulse Tester (DPT). Section 4 presents the measurements performed to the each version of the driver. And finally sections 5 conducts discussion on the data gathered and, finally, section 5 shows the conclusions of the work.

PROPOSED GATE DRIVER
This section presents the working principles of the proposed PSW gate driver using low voltage GaN HEMTs to control a 1200V SiC MOSFETs. The structure of an SiC MOSFET is such that the gate forms a non linear capacitor [20]. Charging the gate capacitor turns the PSW on and allows current to flow between drain and source terminals, while discharging it turns the device off and a large voltage may then be blocked across the drain and source terminals. The minimum voltage when the gate capacitor is charged and the device can just about conduct is the threshold voltage (V T H ). For operating an SiC MOSFET as a switch, a voltage sufficient larger than V T H should be applied between the gate and source terminals. Figure 1 shows a simplified schematic of the proposed gate driver, an elementary inverter leg structure is made of GaN transistors Q H and Q L connected in series between two power supplies V ON and V OF F . The central point of the leg, labeled as "G" in the Figure 1, is connected to the gate of the PSW. When Q H or Q L are on resistors R GH and R GL respectively limit the charging current flowing to the gate thus controlling the V GS slew rate and therefore the PSW turn-on / off time. The inductor L G models the parasitic inductance of the connection to the PSW gate terminal, minimized as much as possible in the design of the PCB.

Gate driver topology
Gallium Nitride HEMTs EPC-2012 from EPC [21] have been selected as the current booster switches (Q H and Q L ) due to their high continuous drain current I D , their high blocking voltage rate V DSS , and their low On-Resistance R DS ON . Moreover these transistors presents a fraction of the input capacitance C ISS to the controller in comparison with Si options. Finally their small footprint allows a compact circuit design. to the gates of the transistors Q H and Q L respectively, reducing the ringing in their gates and lowering the electromagnetic emissions, ensuring a fast transition of the devices while operating them in a secure condition. The voltages of the isolated power supplies used to actually charge and discharge the gate of the PSW where selected to improve its performance. To turn on the PSW V ON = 20V is used, lowering to the minimum the on resistance (R DS−ON ), thus reducing the conduction losses. On the other hand V OF F = −5V was selected to turn off the PSW increasing the noise immunity of the gate of the power device.
Operation of the GaN booster stage is achieved using a dedicated controller unit. The unit reads the input signal IN and the dead-time configuration t D and generates two complementary non overlapping control feeds. These feeds, with the dead-time already injected, are transmitted through the isolation barrier using two high speed Aluminium Gallium Arsenide (AlGaAs) optocouplers. The transmitted signals are sourced into a COTS half bridge controller which finally turns on and off the GaN transistors using a V GS of V DRIV E /0V respectively. For this particular work V DRIV E is 5V .
Currently GaN HEMTs lacks of a commercially available complementary device. Therefore, to control Q H , the half-bridge controller must shift V DRIV E voltage and reference it to the source terminal of Q H which commutes between V OF F and V ON . The t D is an 8-bit digital input that configures the dead-time (in steps of 20nS) that is injected in between the state transitions to avoid the undesired shot-through effect in the GaN half-bridge. During the dead-time both Q H and Q L are off, and the conduction state of the PSW is retained until it's extinguished. This effect is shown in Figure 2, the shaded zones of the diagram represent the dead-time and its effect in the conduction status of the PSW.

Operation stages
During a full switching cycle of the PSW the driver circuit goes through four specific stages. A detailed description of the driver operation is shown in Figure 3.
− Stage-1-(S1): signal IN is low and the V GSL of Q L rises to V DRIV E , turning the device ON. Q H remains in OFF state (V GSH = 0V ) and the voltage across V GS−P SW of the PSW is V OF F . During this stage the capacitance C ISS = C GD + C GS is discharged through R GL leaving the PSW in OFF state with no current flow allowed.

EXPERIMENTAL RESULTS
To evaluate the performance of the proposed GaN current booster a prototype was built and tested. Furthermore, for comparative purposes, two variants of the same topology were built one using Si bipolar junction transistor (BJT) FZT1053A [22] and its complementary device FZT951 [23] both from Diodes Inc. and the other one using Si MOSFETs NDT3055 [24], Table 2 describes the main characteristics of each variant.
In order to measure the switching transients and the power losses of the driver and the PSW, a fully configurable Double Pulse Tester (DPT) board [25] with an inductive load was used. This configuration is shown in Figure 4, the dashed box indicates the device under test (DUT). The active device of the DPT is kept unchanged during all the tests. To ensure fast interchangeability and stability in the testbench each tested circuit was designed and built using the same connection footprint.  The load inductor L Load was manufactured with an inductance of 505µH with an air core to avoid saturation. An ultra fast SiC schottky diode [26] was chosen as a free wheeling diode D F W . The bus capacitance C BU S is composed of a multilayer ceramic and metalized polypropylene film capacitors stack which totalize a capacitance of 5µF with a maximum rated voltage of 1200V . The PSW used in the DPT is the SiC MOSFET CMF10120D from CREE [27]. Its key parameters are shown in in Table 3. Table 3. CREE CMF10120D transistors key parameters list [27] Parameter The test was carried out aplying two pulses of different durations on the gate of the PSW. To set the drain test current of the PSW to I D = 22A a current build-up pulse with a duration of T buildup = 20µS was used with a bus voltage of V BU S = 580V . Finally, the turn on time was T ON = 2.5µS, and the operation frequency was defined as f sw = 125KHz with a duty cycle D ∼ 30%. During the measurements the test circuit remains unchanged, only the gate driver is replaced to comapre each variant. All voltage measurements were performed using a Tektronix THS3014 with four isolated floating channels oscilloscope. As a current transducer a Pearson Electronics INC. current monitor Model: 2878 [28] was used. During the realization of the measurements all the best practices described in [29] were enforced. Figure 5 (a) shows the V GS voltage of each transistor at the output stage in the GaN based driver during the current build up pulse. During the dead-time periods in S2 and S4 both switches, Q H and Q L , are off avoiding the shoot-through effect in the GaN half bridge leg. Also it is possible to see that drive voltage level for Q H is lower lower than for Q L due to the effect of the bootstrap diode of the half-bridge controller. Figure 5 (b) exhibits the voltage signal generated by the gate driver with the dead-time already injected showing that the dead-time has no direct influence in the pulse conformation.  Figure 6 shows the drain-source current I DS , drain-source voltage V DS and instantaneous power P D during the turn-on transient of the PSW for each driver technology. Because of the inductive nature of the load used in the DPT, at the start of the test pulse, the freewheeling diode D F W conducts the full test current. The PSW current I D shown in Figure 6 (a) increases displacing the D F W current while the PSW drain voltage V DS , shown in Figure 6 (b), is clamped to the bus voltage V BU S because of the conducting freewheel diode. When the PSW conducts the test current in full, D F W is recovered and blocked. Afterwards the voltage V DS falls down to the on-state level. The instantaneous power dissipated in the PSW was obtained combining V DS and I DS and the result is shown in Figure 6 (c). The shape on each curve is mostly triangular and compatible with an inductive switching. A summary the measurements during the turn-on stage is detailed in Table 4.    Figures 7 (e) and (f) show the instantaneous power dissipated in the PSW and in the same way than during the turn-ON transient it presents a triangular shape compatible with a pure inductive switching. A summary of the measurements during the turn-off stage can be found in Table 5.

PSW switching energy and driver losses
The switching action of the PSW and the driver itself result in unavoidable losses. The operation of turning on or off the PSW involves the charging and discharging process of the gate capacitance and, therefore, a certain amount of charge has to be transferred. The power lost due to the driving the PSW input capacitance process is dissipated in the output stage components of the gate driver circuit formed by R GH , R GL , Q H and Q L and is computed as Output losses. To accomplish this operation the control stage has to command the output devices Q L and Q H during the switching process, hence dissipating energy. The power dissipated during the control operation is accounted for in the control losses. The driver power losses are summarized in Table 6. In addition to this the switching energy of the PSW during a full period is 470µJ within 1 ± % despite the gate driver technology.

DISCUSSION
This section discusses the results obtained on the bench tests of the PSW using the proposed GaN based gate driver and compares it against their Si based BJT and MOSFET counterparts.  Figures 6 and 7 show the voltages and currents in the PSW when is turned on and off using the GaN, BJT and MOSFET drivers. GaN and BJT drivers produce similar voltages, currents and instantaneous power signals. During the turn-on process the rise times of I DS are similar to the V DS taking 20ns to reach the test current and 21ns to achieve full voltage swing, with a total time of 41ns. During the turn-off process the PSW drain current fall time achieves 7ns, while it takes 12ns and 13ns to the GaN and BJT drivers respectively to block the PSW and withstand the full test voltage totalizing a turn-off time of 19ns for GaN driver and 20ns for the BJT variant. Nevertheless, the PSW shows a slower behavior under the control of the MOS driver taking 25ns, a 25% more time, to the device to achieve the test current. Due to the inductive load, the V DS transient start is delayed increasing the total turn-on switching time in 10% totalizing 45ns. During the turn-off the PSW takes 13ns to block the voltage and 9ns to reduce the I DS to zero computing a turn-off time of 22ns. Figure 8 shows that the MOS gate driver produces a slower V GS slew-rate in the PSW unlike GaN and BJT drivers that exhibit a similar performance. As the output transistors on each driver were selected to have similar current and blocking voltage capacity, the drive strength of each driver implementation is actually limited by the external resistor, R GH or R GL , depending on the transition, plus the contribution of the PSW internal resistor R G . As shown in Figure 9 (a) when the driver switches from S2 to S3, to turn on the PSW, Q H charges the output capacitance composed of C QL OSS and C P SW ISS . Conversely in Figure 9 (b) when the driver switches from S4 to S1, turning off the PSW, Q L discharges the gate capacitance, made up by C QH OSS and C P SW ISS . In Table 7 summarises the output capacitance of the transistors used, it is possible to see that during the S2 → S3 transition, the driven gate capacitance using the GaN driver is 25% smaller than the MOS version, and 50% smaller than the BJT option. In the same way, during the S4 → S1 transition, the driven gate capacitance the GaN solution is 30% smaller than the MOS, and 23% smaller than the BJT. Furthermore, both MOS and GaN driver half-bridge controllers use a supply voltage of V DRIV E = 5V for the output stage in addition to a bootstrap capacitor to operate the high side of the leg with the consequence of reducing the overdrive. While this voltage proves to be sufficient to turn-on the EPC2012 it's not enough for the NDT3055 MOSFET which typically needs 10V of VGS to operate at its full electrical characteristics therefore slowering the V GS rise-time in the MOS driver. Despite the downgraded performance of the MOS driver, all three circuits produce almost the same switching energy loss in the PSW under the same operation condition. These results are consistent with the switching energy informed in the PSW's device datasheet [3]. The slightly increase in switching loss of the MOSFET version is related to its slower performance, but is neglectable in comparison with the absolute energy value.

Driver loss assessment
The Output Power of each driver show similar losses on each technology variant. BJT exhibits a reduction in 25% on the output loss due to the scatter of the on-resistance R CE ON on each device of the

CONCLUSIONS
A GaN based gate driver was proposed, simulated and experimentally validated in an inductive hard switching environment using a DPT bench with a state of the art SiC MOSFET as active device. Its performance was compared against similar solutions using Si based BJT and MOSFET transistors and during all the evaluations the PSW shows equivalent performance with almost equal switching losses. This is explained since the switching process is dominated by the external gate resistors R GH and R GL neglecting the effects of the on-resistance of the driver output transistors. All three drivers show similar output losses due to the fact that ❒ ISSN: 2088-8694 the transistor for each driver were selected with similar electrical output characteristics. On the other hand the GaN driver control loss is negligible in comparison with the BJT and MOS variants relaxing the requirements of the control logic. Finally the GaN based output stage is 12 times smaller. This area reduction in addition to enhanced characteristics of the GaN material makes this option suitable to integrate directly in a dedicated power module reducing the circuit parasitics ACKNOWLEDGMENT This work is a PhD Thesis supported the Facultad de Ingeniería of the Universidad de Buenos Aires and by the "UBACYT 20020170100386BA" research subsidy titled "Nuevas estructuras y técnicas de simulación y control para convertidores estáticos y generadores de pulsos" from the same university.