A dual-switch cubic SEPIC converter with extra high voltage gain

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INTRODUCTION
Numerous applications for high step-up DC-DC converters have been reported so far, such as renewable energy systems (photovoltaic, wind, fuel cells, automotive industry, industrial applications, computer, uninterruptible power systems, telecommunications. The development of new power electronics circuits, in order to satisfy all these needs, is a topic of great interest, where the trends are wide conversion gains, high power density, improved efficiency and low cost [1], [2]. Typically, the 48 V DC of the battery bank has to be boosted to a 380 V in order to be connected to the DC bus in the information and telecommunication industry and the high intensity discharge (HID) lamps for automobile head lamp require at their start-up the increase of voltage from the battery's 12 V to more than 100 V, at 35 W power [3], [4]. The output voltage of fuel cells is very low. Then, a step-up DC-DC converter must follow a fuel cell stack in order to realize a useful power supply [5]. The photovoltaic arrays are sources with low output voltage. Moreover, the output voltage can be affected either by the weather or the partial shading. Series connections of photovoltaic cells or arrays are not actually a practical solution to obtain wide voltage. Thus, for grid connected applications, DC-DC converter needs to boost that low output voltage to high voltage [6], [7]. The interconnection of low voltage energy sources onto the higher voltage is difficult task. The conventional basic converters to achieve such a wide voltage gain, would lead to operate with extremely high duty ratio, higher than 0.9 (D>0. 9). An extreme duty cycle impairs the efficiency and seriously affects the dynamic behaviour of the converter by imposing obstacle for transient response [8]. However, a very fast comparator, which is expensive, is required into the control loop in order to produce an extreme duty cycle. The extreme duty ratio may even cause malfunctions at high switching frequency due to the very short conduction time of the diode in step-up converters [8]. Also, they force fruitfully short off-times or low switching frequencies, which produce a severe diode reverse-recovery current and then, will increase the electromagnetic interferences (EMI) level. Low switching frequency causes higher ripple current and increases magnetic components [9]. Moreover, the voltage conversion gain is limited by the effect of power switch, rectifier diodes, parasitic resistances of inductor and capacitor, and saturation effects of the inductors and capacitors [8].
Several technologies and topologies of DC-DC converters to provide wide voltage gain are reported in the literature. The extreme high duty ratio operation could be avoided and the high step-up voltage achieved by using either isolated or non-isolated DC-DC converters. The isolated converters can provide high voltage gain by adjusting the turn's ratio of the high frequency transformer or the coupled inductors. However, they suffer high voltage spike, high circulating current and high voltage stress on output semiconductors caused by the leakage inductor [10]- [13]. The non-isolated converters can provide high voltage gain, either by increasing the turn's ratio of the coupled inductors or by the permutations and combinations of the various voltage booting techniques [14]. Many non-isolated and isolated step-up DC-DC converters have been reported in the literature [1], [14]- [16]. A classification of non-isolated with high gain DC-DC converters operating in CCM has been presented in [1]. In [1], step-up topologies with wide conversion ratios have been sorted into five types, namely: (1) cascaded boost converters, (2) coupledinductor based boost converters, (3) switched capacitor based boost converters, (4) interleaved boost converters, and (5) three-state switching cell (3-SSC) based converters.
To achieve a high step-up voltage gain using non-isolated topologies without any magnetic coupling, the voltage boosting techniques have been used [14] has presented a categorization of voltage boosting techniques. They have been classified into five types, namely: (a) switched capacitor (charge pump), (b) voltage multiplier, (c) switched inductor and voltage lift, (d) magnetic coupling, and (e) multistage/-level structures. This categorization gives a view on how most of high step-up converters are constructed. Thus, in the purpose to enlarge the voltage gain and ameliorate the converter performance and efficiency, a number of converter arrangements have been derived and reported in the literature [14]- [16]. Basic boost DC-DC converters combined with voltage multiplier cells have been proposed to get families of converters possessing higher voltage gain in [17], [18]. In [19]- [21], basic DC-DC boost converters and switched capacitor/switched inductor structures have been combined to improve the voltage conversion gain. [22]- [24] have used the voltage lift technique with classical boost converters to achieve wide voltage ratios. The authors in [25]- [31] have substituted for inductors in the classical boost converter with voltage multiplier cells and obtained quadratic voltage conversion gains.
This paper proposes a dual-switch cubic SEPIC converter exhibiting an extra high voltage gain and moderate voltage stress on semiconductor switches. It consists of a voltage multiplier cell (VMC) and the hybrid SEPIC DC-DC converter in [19]. The proposed converter is a non-isolated converter without any magnetic coupling having a cubic dependence on the duty cycle D. The proposed converter has a higher voltage gain compared to the conventional and quadratic boost converters. The proposed converter has the following merits: − Cubic dependence on the duty ratio allowing it to provide wide output-to-input conversion range at moderate duty cycle without any magnetic coupling, − Relatively reduced voltage stress on active and passive switches except the output switches S 2 and D o for 0.5<D<1, − The input and output terminals share a common ground. This paper is organized as following: section 2 presents the structure and the operating principle of the proposed converter, section 3 details the steady-state analysis of the proposed converter, section 4 provides the efficiency analysis with parasitic parameters considered, the comparison with some quadratic converters is done in section 5, section 6 discusses the extension of the proposed converter so that the voltage stress on the output switches drops, section 7 presents the simulation results and section 8 concludes the paper.

PROPOSED CONVERTER AND OPERATING PRINCIPLE
The dual-switch cubic SEPIC converter is derived from the new hybrid SEPIC converter, despicted in Figure 1, by inserting in cascade between the input inductor and the main switch, a voltage multiplier cell as shown in Figure 2(a). The additional components allow the proposed converter to operate differently from the hybrid SEPIC Converter. The steady-state waveform under continuous conduction mode (CCM) and discontinuous inductor current mode (DICM) Operations is depicted in Figure 3 and, the corresponding modes are shown in Figure 2. To analyse the steady-state characteristics of the proposed converter, some conditions are assumed as follows: i) All components are ideal, ii) All capacitors are sufficiently large, and the voltages across the capacitors can be treated as constant.
For ease the analysis, the proposed converter is assumed to be lossless, so P in =P out is held. Hence, the ESRs of inductors and capacitors and losses of the semiconductor's devices such as switches and diodes are not considered.

CCM operation
In CCM, the dual-switch cubic SEPIC converter goes through two topological modes, defined as modes 1 and 2, as shown in Figure 2(b) and (c) in each switching period.
Mode 1: At t = t 0 = 0, both power switches S 1 and S 2 are turned on, and diode D 1 is turned on, while diodes D 2 , D 3 , and the output diode Do are reverse biased, as shown in Figure 2(b). The currents through inductors L 1 and L 2 and, output inductor L o increase linearly. The energy stored in the capacitor C is released to the inductor L 2 , and the energy stored in the capacitors C 1 is released to the output inductor L o , while the output capacitor C o is supplied the load. Some of the main equations among the components in this mode are given as (1), Mode 2: At = 1 = , both power switches S 1 and S 2 are turned off, and diode D 1 is reverse biased, while diodes D 2 , D 3 , and the output diode Do are forward biased, as shown in Figure 2(c). The currents through inductors L 1 and L 2 decrease linearly. The energy stored in the output inductor Lo is released to the output capacitor C o and the load, while the energy stored in L 1 and L 2 with the source energy V in are released to charge the capacitors C and C 1 . Thus, the voltages across L 1 , L 2 and L o , the currents through C, C 1 and C o are given as (3), and (4)

DICM operation
In DICM, the operating modes can be divided into three modes defined as modes 1, 2, and 3. Mode 1. The operating principle is the same as that for mode 1 of the CCM operation. Mode 2. The operating principle is the same as that for mode 2 of the CCM operation. Mode 3. At = 2 = ( + 2 ) , both power switches S 1 and S 2 are still turned off, and diode D 1 is still reverse biased, while diodes D 2 , D 3 , and the output diode Do are turned off, as shown in Figure 2(d). The energies stored in inductors L 1 , L 2 and L o are zero. Thus, only the energy stored in C o is discharged to the load.

STEADY-STATE PERFORMANCE ANALYSIS OF THE PROPOSED CONVERTER
By using the volt-second balance principle on inductors and ampere-second balance principle on capacitors, the following equations are derived as (5),

Ideal voltage conversion ratio in CCM
By solving (5), the output voltage and the voltages of the capacitors can be derived as, Hence, from (9), the ideal voltage conversion gain is given by (10); According to (10), the ideal voltage gain of the proposed converter is a cubic function of the duty cycle D. So, this converter can provide wide voltage conversion ratio range. Moreover, the proposed converter can operate either in step-up mode or in step-down mode. If the duty cycle D>0.317, the voltage gain is greater than 1, it operates in step-up mode. Otherwise, it operates in step-down mode.

Ideal voltage conversion ratio in DICM
By solving equations from volt-second balance principle on each inductor, we derive the voltages of capacitors and the ideal output voltage as (11) is equal to the average load current . Thus, By substituting (12) into (14), we get; Then, the normalized inductor time constant is defined as (16); By substituting (15) into (12), the voltage gain is given by (17)

Boundary operating condition between CCM and DICM
In boundary conduction mode (BCM), the voltage gain of the CCM operation is equal to the voltage gain of the DICM operation. From (11) and (20), the boundary normalized inductor time constant can be derived as (18); The Dual-Switch Cubic SEPIC converter will operate in CCM if is larger than . It will operate in DICM if D 2 <(1-D), that is, <(1-D) 2 .

Voltage stresses on power switches and diodes
The voltage stress on the semiconductor components is calculated during their turn-off state. The normalized voltage stresses on S 1 , S 2 , D 1 , D 2 , D 3 and D o are derived as (19) and (20), The normalized voltage stresses on the active and passive switches of the Dual-Switch Cubic SEPIC converter are plotted in Figure 4. Since the proposed converter can achieve high voltage gain when the duty cycle ratio lies in the range 0.5<D<1, the voltage stresses on semiconductor switches, except for output passive switch D o , are less or equal to the output voltage as shown in Figure 4.

Current stresses on power switches and diodes
From the charge balance (6), the average currents of the inductors L 1 , L 2 and L o , namely, 1 , 2 and can be calculated as (21), (22), (23), The normalized DC current stresses of the two power switches (S 1 and S 2 ) and the four diodes (D 1 , D 2 , D 3 and D o can be derived as (24) and (25)

Currents of the inductors
The peak-to-peak current ripples of the inductor currents 1 , 2 and can be given as (26), (27), and (28), where is the switching frequency.

Voltages of the capacitors
The peak voltage ripples of the capacitor voltages , 1 and 0 can be deduced as (29)

EFFICIENCY ANALYSIS CONSIDERING THE PARASITIC PARAMETERS
The theoretical analysis above is based on ideal components, i.e. without parasitic parameters. However, the design of converter must consider inductor and capacitor copper losses due to the ESRs of inductors and capacitors, respectively, power loss in the active switches and power loss in the passive switches. In order to facilitate calculations, the voltage and current ripples of inductors and capacitors are neglected.

Power losses of inductors
The loss in the inductors consists of the copper loss and the core loss. The inductor copper loss is caused by ESRs 1 , 2 and of inductors L 1 , L 2 and L o , respectively, and can be deduced by, (1− ) 4 From [30], the core loss in the magnetic circuit of inductors is deduced by,

Power losses of capacitors
The capacitor copper loss is caused by ESRs , 1 and of capacitors C, C 1 and C o , respectively. The rms of currents , 1

Power losses of power switches
The power loss in the power switches is divided into two parts: the conduction loss and the switching loss. The conduction loss occurs during the ON-state caused by the ON-resistances 1 and 2 of the power switches S 1 and S 2 , respectively, and can be calculated as (39), The power loss due to the threshold voltage of the diodes is expressed as (46) Hence, the overall power loss in the diodes gives = + (47)

COMPARISON WITH SOME QUADRATIC CONVERTERS
The comparison, in order to verify some key steady-state features of the dual-switch cubic SEPIC converter with some quadratic converters in the literature, namely, the number of components, voltage gains and voltage stresses of the switches and diodes is presented in Table 1. From the Table 1, the proposed converter utilises the same number and the higher number of components, respectively, with the converter in [29] and the converters in [19], [31]. However, it has the widest voltage conversion gain for 0.5<D<1 with the same input voltage, as shown in Figure 5. Compared to the the converters in [29] and [31], the proposed converter has the lower voltage stresses on their switches and diodes for the duty cycle lies in the range 0.5<D<1, except the output diode D o .  Figure 5. Ideal voltage gain M as a function of duty cycle D

EXTENSION OF THE DUAL-SWITCH CUBIC SEPIC CONVERTER
The extension of the dual-switch cubic SEPIC converter improves the voltage gain and reduces the voltage stresses across the output switches. It is obtained by adding a voltage multiplier rectifier which consists of diode and capacitor at its output as shown in Figure 6. It shall be noted that the voltage gain can further be improved by inserting additional voltage multiplier cells. The voltage gain of the extension of the dual-switch cubic SEPIC converter can be easily derived as The normalized voltage stresses on output switches S 2 and D o of the extended proposed converter are derived as

SIMULATION RESULTS
The proposed converter in Figure 2(a) has been simulated using MATLAB/Simulink to validate the theoretical results that were obtained in Section 2. The proposed converter is simulated for the following specifications: = 20 , = 400 , = 280 and = 40 . The nominal voltage conversion ratio and the duty ratio from (11) are: = 20 and = 0.676, respectively. The values of the passive components have been selected based on (26), (27), (28), (29), (30) and (31), then calculated for ∆ / = 1% and ∆ / = 1%. The simulations have been done using the following values: 1 = 250 , 2 = 2.5 , = 15 , = 150 , 1 = 22 , = 2.2 and = 570 Ω. Figure 7 and Figure 11 present the simulated output voltage and current waveforms with average voltage of 400 V and 0.7 A respectively, for an input voltage of 20 V which is in accordance with the specifications. Figure 8, Figure 9, and Figure 10 show the simulated inductor current waveforms 1 , 2 and , which show that the converter works in CCM. Moreover, the average currents 1 , 2 and are 14 A, 4.5A and 2.2 A respectively, which are in accordance with the obtained values from the analytical (21), (22) and (23). These results were expected from the analysis, and show the feasibility of the proposed converter. respect to their voltage gains, voltage stresses on the switches and diodes, and numbers of components. The characteristics of the converter are as following: a) The proposed converter has a cubic dependence with respect to the duty ratio that allows them to provide extra high voltage conversion gain which is an operable solution for high voltage applications, and also helpful to reduce the current stress through the switches. b) The voltage multiplier cells are important to obtain the voltage gain that the system required, also, to reduce the voltage stress on semiconductors switches. Then, the efficiency is improved. c) The voltage stresses on the switches and the diodes of the proposed converter are relatively low compared to some quadratic converters. In order to validate the theoretical analysis, MATLAB simulation has been achieved and the simulation results have been provided. These results support the theoretical analysis and speak the feasibility of the proposed converter.