A finite set-model predictive control based on FPGA flatform for eleven-level cascaded H-Bridge inverter fed induction motor drive

Received Nov 12, 2020 Revised Mar 16, 2021 Accepted Apr 9, 2021 Model predictive control has been considered as a powerful alternative control method in power converters and electrical drives recently. This paper proposes a novel method for finite control set predictive control algorithm for an induction motor fed by 11-level cascaded H-Bridge converter. To deal with the high computation volume of MPC algorithm applied for CHB converter, 7-adjacent vectors method is applied for calculating the desired voltage vector which minimizes the cost function. Moreover, by utilizing field programmable gate array (FPGA) platform with its flexible structure, the total execution time reduces considerably so that the selected voltage vector can be applied immediately without delay compensation. This method improves the dynamic responses and steadystate performance of the system. Finally, experimental results verify the effectiveness of control design.


INTRODUCTION
Model predictive control has the potential to improve the performance of fast dynamical system as power converters and electrical drives [1]- [7], due to its considerable merits: intuitive concept, ability to handle nonlinear MIMO system with input and state variable constraints. The concept of MPC is model base control strategy as a typical case of optimal control theory, in which the future behaviour of the system is predicted over a predefined horizon to achieve several important goals in cost function. The MPC firstly developed in process industry related to its high computation burden, however along with the development of micro-processor like DPS or FPGA, the application of MPC has extended for nonlinear system with fast dynamic behavior. In electrical drives area, MPC has been successfully applied for some kinds of motor as induction motor [8,9], brushless DC motor (BLDC) [10], permanent magnet motor (PMSM) [11]. Besides, power converters which have finite switching states are suitable for FCS-MPC. In this field, MPC has several applications for both VSI converter [12,13] and several structures of multilevel inverters: NPC [14], [15], Ttype [16], [17], CHB [18]- [22], matrix [23].
The multilevel converters have been researched widely nowadays due to its high-quality output voltage whilst the device voltage stress and switching frequency are significantly reduced, especially in highpower and medium voltage application [24]. Among diverse multilevel converter topologies, the CHB structure which owns the modularity and flexible construct with different voltage level is the most successful topology. The common problem of multilevel converters is the complex modulator when the number of converter level increases. Hence, to implement FCS-MPC for multilevel CHB converter supplied for an induction motor, a method using 7-adjacent vectors [25] is applied to reduce the computation volume. In combination with eliminating PWM algorithm and utilizing FPGA platform [26][27][28][29], the predictive control method can be simply solved with small execution time and the selected voltage vector can be employed immediately, which improves dynamic response of inner control loop considerably compared to the conventional PID controller. Thus, other goals can also be obtained base on the given cost function, such as optimal switching devices and minimal common-mode voltage. Various experiment scenarios are implemented to evaluate the efficiency of the proposed FCS-MPC control design for IM drive fed by CHB inverter.

Overview of CHB inverter
A power cell created by single-phase H-Bridge inverter is called as a basic component of cascaded H-Bridge converter. In this paper, prototype of eleven-level CHB converter is utilized with typical configuration as Figure 1. Each phase consists of five cells in series connection and an dc voltage source V dc is supplied for each cell . The switching states of a phase can generate three cell state S xi = {1, 0, -1} corresponding to three voltage levels {+V dc , 0, -V dc }, where x represents phase a, b or c. The voltage level of a single phase 11-level inverter is obtained by.  ;;

Cascaded H-Bridge space vector
A three phase eleven-level CHB inverter is applied in this research. The space vector in αβ coordinate of the chosen topology consists of total 1331 combinations of voltage state, Figure 2. To balance three phase voltages, all the redandunt states of a voltage vector producing high common mode voltage is neglected, which means only 331 candidate voltage vectors are apllied.

Predictive currents of induction motor
The mathmetic model of an induction motor in αβ coordinate is presented by.
where ss RL , are stator resistor and inductor, rr RL , are rotor resistor and inductor, respectively. The vector forms of the current and flux of the stator and rotor of the motor is given as (5).
The (3) and (4) in which For MPC control design, forward-Euler method is applied to transform the continuous-time model (8) transformed into discrete-time model.
with Ts is sampling time and.
The stator currents in N steps ahead can be predicted as.

CONTROL METHOD 3.1. Predictive current control design
The block diagram of control design in this paper is presented in Figure 3, which includes four main blocks: 11-level CHB inverter (1), control strategy (2), current measurements (3) and induction motor with encoder (4). In control strategy, the d-coordinate reference stator current is generated by the flux regulator, meanwhile the speed regulator output is the reference current in q-coordinate. These reference variables are transformed into αβ coordinate and applied for inner predictive current control. The appropiate voltage vector is selected from the space vector to minimize a cost function of stator current errors.
Optimal swiching in the next section, computation volume is still extremely high. In order to deal with this problem, the 7 adjacent vectors method is used in this paper, where only 7 vectors which are adjacent the employed vector in the previous period is used to compute in the cost function [17]. This method reduces considerably the volume of calculation for predictive control the 11-level CHB converter. The FCS-MPC algorithm for every sampling control period in detail is shown in Figure 4. In addition, optimal devices switching in each phase can be achieved by appling the switching sequence presented in Figure 5. Phase A is taken for example, when the voltage level S a of phase A increases or decreases by 1, only one cell state S ai is changed in five cells of phase A. This method reduces the number of devices switching to reduce the switching losses.

Cost function selection
The main purpose of cost function in this paper is minimal error between the predictive current and the reference stator current in αβ coordinate.
In usual, when the calculation time is significant in comparison with control period, the delay compensation is applied to enhance the control performance [25]. However, by using FPGA, the calculation time in this research is considerably reduced, which allows the chosen voltage vector can be employed immediately after finishing calculation in the same control period, instead of waiting and apply at the beginning of the next period, as shown in Figure 6. Therefore, the dynamic response of system is improved due to the power of FPGA. The cost function in this research is given by.   In detail, Clk and rst are synchronous clock system and reset signal for all states and variables of an IC, respectively. In most of execution time, FPGA computes the control algorithm in parallel. Init signal allows the IC to operate while the done signal confirm that IC has finished its operation. To implement sequential calculation in FPGA, the init signal of an IC is set by the done signal of the previous IC in only one clock system. Since an IC operates in only a small predifined time and will be disable in almost the time, this implementation method avoids the propagation of unexpected glitches and reduces the FPGA power consumption.
The algorithm control is built in FPGA with multi ICs as presented in Figure 8 with Zybo Z7-20 device. The clock system is 100MHz, and the sample time for outer and inner controller are 1ms and 50us, respectively. The data for the cost function is calculated sequentially from the measurement signal. Then the cost function is implemented in parallel to reduce the calculation time.
The execution time to read ADC and implement control algorithm is measured exactly by software for each IC shown in Figure 9. The total execution time for the controller is 3.85us as shown in oscilloscope, which is negligible in comparison with the sampling time of 50us.  . .

EXPERIMENT VERIFICATION 5.1. Experiment system
An experiment system is built to validate the FCS-MPC control algorithm for induction motor fed by 11-level CHB converter as shown in Figure 10. In detail, the force board of a single cell and the measurement circuit is presented Figure 11 (a) and Figure 11 (b), respectively. The control design is embedded in a FPGA card called ZYBO-27 and the control object is a Siemens induction motor with the parameter given by Table 1.

Result and discussion
Various experiment scenarios are conducted to evaluate the proposed FCS-MPC applied to IM drive. The experimental results are collected and displayed by software and ossiloscope. First, the dynamic current response of the controller is verified by sudden change the q-reference current value of {1A, 0A, -1A} at various moment, while d-reference current is set at 1.5A. The result illustrates that current in qcoordinate i sq can track the reference quickly in 2.35ms in Figure 12. At the same time, i sd keeps constant at 1.48A and i αβ tracks the reference in 6.5ms with 1.5% current ripple, presented in Figure 13 and Figure 14, correspondingly.
In the second scenario, the transient response of the control system with the constant load is tested. The reference of rotor speed changes among several values from 0 to 200rad/s and including speed reversal. As can be observed in Figure 15 the rotor speed also quickly tracks the reference in 0.1s with negligible tracking error. The current in αβ is controlled stably with small current ripple, as shown in Figure 16. In addition, while the motor speed changes from 1800 rpm to 1200 rpm, the phase voltage vector V an changes from 11 downto 9 voltage levels in Figure 17, respectively. Other performances of cost function are evaluated. Figure 18 compares two-pulse pattern for two below valves S 2 and S 4 of all 5 cells in phase A. The results prove the efficiency of method in reduce switching amount as well as the switching losses.
Finally, Figure 19 validates the effectiveness of using 331 candidate voltage vectors. The peak value of V zn is only about 30.4V, approximately to 2 3 , which ensures the voltage balance among three phase and increases the stability for the system.

CONCLUSION
In this research, a novel solution to implement the predictive current control for IM drive fed by 11level CHB inverter is proposed. In every consecutive sampling period, a subset of 7-adjacent voltage vector of the previous employed vector is utilized to predict the future stator current in one step ahead. Due to the parallel computation ability and flexible structure of FPGA, the calculation time is reduced significantly (only 3.85us). The selected vector for minimizing cost function can be employed as soon as finishing execution time for control algorithm. Achieved experimental results verify good performance of proposed method not only in dynamic response but also in steady-state.