A new multilevel inverter topology based on switched-capacitor technique

Received Oct 13, 2020 Revised Feb 13, 2021 Accepted Feb 20, 2021 This paper presents a new multilevel inverter based on the switchedcapacitor technique. The topology aims for renewable energy and fuel cell applications that demand high magnitude output ac voltage. This configuration of the inverter can produce a total of thirteen voltage levels using a single DC source. The topology features voltage boosting with a triple gain of the input voltage source without utilizing a boost DC-DC converter. Furthermore, the voltages of the capacitors are self-balanced at any desired voltage level during each cycle. Therefore, auxiliary circuits are no longer needed. A comparative study of the presented inverter with the classical topologies and recently introduced topologies has been done in power switches, driver circuits, blocking voltage of the switches, and boosting the input voltage. A simple fundamental switching scheme is applied to the proposed topology to validate the viability of the topology.


INTRODUCTION
Multilevel inverters (MLIs) have become very popular and globally recognized for numerous industrial applications such as renewable energy systems, motor drives, Induction heating, electric vehicles, FACTs devices, active power filtering, and many more. MLIs possess numerous advantages compared to classical two-level inverters, such as decreased total harmonic distortion (THD), lower voltage stress across switches, and electromagnetic interference (EMI). The basic principle of MLIs is to generate a staircase voltage waveform near to sinusoidal with high power quality. The desired staircase voltage waveform is synthesized using an appropriate combination of different switches, reducing power switches' voltage stress and total harmonic distortion (THD) [1]- [4].
Generally, well-established classical MLIs are categorized into the following three main types: Cascaded H-Bridge (CHB), Neutral-Point Clamped (NPC), and Flying-Capacitor (FC). NPC MLIs are widely used in the industry. However, high-level NPC inverter structures require several clamping diodes and capacitors' balancing involving auxiliary circuits and sensors, making the system more complicated, less reliable, and more costly to maintain. The FC MLI is another inverter topology with an energy storage facility. The flying capacitors' voltage can be maintained at their respective levels using the topology's switching state redundancies. Thus, the voltage balancing mechanism becomes complicated. It is the prerequisite of too many bulky flying capacitors, and the complex control mechanism for capacitors balancing that limits higher levels on this inverter. The CHB MLIs, on the other hand, consists of several H- bridge cells to produce multilevel output. However, these CHB MLIs are constructed using multiple isolated power sources, which somehow not suitable in many applications such as electric vehicle drives. Moreover, they generally employ more power switches, gate drives and resulting in more power losses. These issues motivate researchers to develop new inverter topologies, and to date, many inverter structures addressing those issues have been introduced in the literature [5]- [15].
Recent MLI topologies [5]- [15] tend to focus on increasing the efficiency and modularity of the MLIs. Hence, most of them have a more straightforward structure [3], but they are buck-type MLIs. They are not able to boost up the output voltage. Typically, a front-end DC-DC boost converter is required, which leading to complex control and structures. The boosting of input voltage should be the essential feature for the inverter topologies used for high voltage and renewable energy systems (RES). One such type of MLIs topologies is the switched capacitor (SC) based MLIs. In general, SC-MLIs contain a single DC source connected in various capacitors' configurations to boost the low input voltage.
Moreover, without any auxiliary circuits, the capacitor's voltage is self-balanced in SC-MLIs [16]. The boosting voltage ability and non-auxiliary circuits for balancing the capacitor voltage are remarkable benefits provided by these SC-MLIs. However, the existing SC-MLIs topologies consisted of many power switches and capacitors with high voltage stress; thus, the overall system becomes problematic, costly with high power losses. Hence, research on developing new SC-based MLIs to use fewer switches and capacitors with low voltage stress progresses [16]- [38].
SC-MLIs presented in [16]- [20] use a back-end H-bridge circuit for polarity change. This inverter exhibits a simple structure with a high number of voltage levels. However, four power switches in those structures must withstand high voltage stress equal to the load's peak voltage. It put limitations on these topologies for higher voltage applications. Other SC-MLI were proposed in the literature [39][40][41]. They require two switches only to withstand the blocking voltage equal to the peak output voltage. However, the voltage blocking rating is still regarded as high.
In this paper, a new SC-MLI topology is proposed. The advantages of the proposed SC-MLI topology include; 1. self-voltage balancing of capacitors without using auxiliary circuits and sensors; 2. Input voltage can boost with a gain of three; 3. a single DC source to generate multiple output voltage levels and 4. low voltage rated power switches. The total standing voltage (TSV) of the SC-MLI will be shown to be at the low side even though fewer components are employed. The design of the proposed SC-MLI will be elaborated on in the following sections. A simple fundamental switching scheme is used for the proposed SC-MLI to generate the 13-level output voltage. Simulation using Matlab-Simulink® software will be performed using different loading. From the results, it will be shown that the design of the proposed SC-MLI is validated.

THE PROPOSED MULTILEVEL INVERTER
The configuration of the proposed inverter topology is depicted in Figure 1. The topology consists of 11 unidirectional switches, a bidirectional switch (S 11 ), a diode, and three switched capacitors. With this inverter configuration, thirteen voltage levels can be achieved. The voltage of switched capacitor C 1 is balanced at a voltage level equal to Vin input voltage. Simultaneously, the input DC source of magnitude V in charges switched capacitors C 2 and C 3 to the voltage level of 0.5Vin. As the capacitor's voltages are selfbalancing in nature, sensors and auxiliary circuits are not required to balance switched capacitors in the presented inverter topology. Figure 2 depicts the pulses to generate a 13-level output voltage. ±0.5V in Voltage level: As shown in Figure 3(a), the switches S 2, S 6, S 8, and S 11 are turned on to produce voltage level 0.5V in . Switch S 4 is turned on; thus, the diode is in forwarding conduction mode. The switched capacitor C 1 is parallel with the input DC source and charges it to V in magnitude. The switched capacitors C 2 and C 3 are also parallel with input DC when switches S 5 and S 7 are turned on. It charges these capacitors to the voltage level of 0.5V in . To produce a voltage level of -0.5V in , the switches S 1 , S 5 , S 7, and S 11 are turned on, as shown in Figure 4(a). The process of charging the switched capacitors will remain the same as in the 0.5V in state. ±1V in Voltage level: As shown in Figure 3(b), the switches S 2 , S 6 , S 8, and S 9 are turned on to produce voltage level 1V in . The switched capacitor C 1 is parallel with the input DC source through S 4 and the diode. The capacitor charges to V in magnitude. The switched capacitors C 2 and C 3 are also in parallel combination with input DC when switches S 6 and S 8 are turned on. It charges these capacitors to the voltage level of 0.5V in . To produce voltage level -1V in, the switches S 1 , S 6 , S 8, and S 10 are turned on, as shown in Figure 4(b). The process of charging the switched capacitors will remain the same as in the 1V in state. ±1.5V in Voltage level: As shown in Figure 3(c), the switches S 2 , S 5 , S 8 , S 11, and S 12 are turned on to produce voltage level 1.5V in . The switched capacitors C 3 is in series combination with input source and discharges. At that moment, there is no effect on capacitor C 2 in this state. Switch S 4 is turned on; thus, the diode is in forward conduction mode. The switched capacitor C 1 is parallel with the input DC source and charges it to the magnitude of 1V in . To produce voltage level -1.5V in, the switches S 1, S 6, S 7 S 11, and S 12 are turned on as shown in Figure 4(c). The process of charging the switched capacitors will remain the same as in the 0.5V in state. In this state, C 3 provides the power to load in series combination with input source and discharges, while C 2 remains not affected. Power switches Capacitors S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 C1 C2 C3 Vin D S1 State 1:Vo=0.5v  Figure 3(d), the switches S 2, S 3, S 5 , S 7, and S 9 are turned on to produce voltage level +2V in . The switched capacitors C 1 is in series combination with the input source to provide the load current and discharges. Simultaneously, there is no effect on capacitors C 2 and C 3 in this mode of operation. To produce voltage level -2V in, the switches S 1, S 3, S 6 S 8, and S 10 are turned on as shown in Figure 4(d). The switched capacitors C 1 discharge as they come in series with the input source. At the same time, there is no effect on capacitors C 2 and C 3 in this state. ±2.5V in Voltage level: As shown in Figure 3(e), to generate the voltage level +2V in, the switches S 2, S 3, S 5 , S 8 S 11, and S 12 are turned ON. The switched capacitors C 1 and C 3 are combined with the input source to provide the load current and discharges. At the same time, there is no effect on capacitors C 3 in this mode of  Figure. 3(f), in this mode of operation to produce voltage level ±3V in , all the switched capacitors C 1 , C 2 and C 3 are combined with the input source to provide the load current and therefore discharges.

Modulation technique and Capacitor Value Calculation
In this paper, the fundamental switching frequency method is used to generate pulses for all the switches. A sinusoidal 50 Hz reference signal is compared with some available DC-voltage levels and generates related pulses for power switches. This switching technique's main advantage is low switching frequency, which significantly reduces the switching losses. Details of the fundamental switching frequency technique are not discussed here.
Generally, the switching angles θ i can be obtained as (1) In switched capacitor MLIs, the capacitor's optimum calculation is one of the most critical issues to retain the capacitor's voltage ripples in an acceptable range. For calculating capacitors' capacitance, the longest discharging cycle (LDC) for each capacitor over a complete output voltage cycle is considered. The capacitor discharges the maximum amount of charge during LDC. The value of discharging charge is dependent on the output current and LDC duration.
Therefore, the maximum discharging amount of the capacitor's charge is obtained by (2)  Where, 0 is the frequency of output waveform, I o is the amplitude of load current, and ω is the corresponding angular frequency. Whereas, [ 4 , − 4 ] is the longest discharging cycle (LDC) of the capacitor C 1 and [ 5 , − 5 ] is the LDC interval of the capacitor C 2 and C 3 . Thus, by assuming ∆V as the maximum allowable voltage ripple over the capacitor, the optimum capacitance values of switched capacitors can be calculated by (4) Table. 2 presents the comparison study with other recently introduced MLIs, considering the capability of voltage boosting and self-balancing of switched capacitors. For generating 13-level voltage, the proposed SC-MLI topology requires the least component counts in power switches and gate drives. Moreover, it is achieved using a single DC source. The other topologies require more switches to attain the same voltage levels. The voltage stress across the power switches in the proposed topology is much lower than the rest topologies. It is clear from the comparison that the proposed topology requires the least number of power switches and blocking voltage compared to other inverter structures. Please be noted that TSV is defined as Total Standing Voltage, which is similar to the total voltage value that needs to be blocked by the power switch during its off state.

RESULTS AND DISCUSSION
Simulations are carried out using the Matlab-Simulink® computer software tool. A single-phase 13level inverter was developed for simulation purposes with different parameters used as tabulated in Table 3. In this work, the fundamental frequency switching method is employed to generate the required gating pulse for the power switches. The selected input voltage source is 100V for simulation purposes, and the resistive load of 150 Ω and the inductive load of 150 Ω and 100m H are used for the proposed SC-MLI. Figures 5(a-b) illustrates the output voltage and current waveforms for the proposed SC-MLI. The output voltage and current have a peak of 297.5 V and 1.9 A, respectively. The voltage is boosted triple times from the 100 V input voltage value. It proves the viability of the proposed SC-MLI. The result with inductive load also confirms the capability of the proposed SC-MLI to operates with bi-directional capabilities. As depicted in Figure 5(c-d), the harmonic spectrum of the output voltage contains 4.65 % THD without using filters, while the harmonic spectrum of sinusoidal output current is having 2.53 % THD. All the obtained results satisfy the harmonics IEEE standards, i.e., IEEE519. The 13 levels at the output with  Figure6 (a). By considering a 10 % voltage ripple, the optimum value of capacitor C 1 obtained is approximately 1200 μF and 1000 μF for capacitors of C 2 and C 3 . The switched capacitors voltages at the rated output and current waveforms are shown in Figure 7. The capacitor voltage of C 1 is maintained at 100 V, while C 2 and C 3 are maintained at 50 V, respectively. The result verifies the self-balancing of all three switched capacitors. The voltage ripples of the capacitors can also be observed. The maximum voltage ripples of C 1 are about 9 V, while capacitors C 2 and C 3 are around 8 V. The blocking voltage of each switch in the inverter is shown in Figure 6