Improved 25-level inverter topology with reduced part count for PV grid-tie applications

Radouane Majdoul, Abelwahed Touati, Abderrahmane Ouchatti, Abderrahim Taouni, Elhassane Abdelmounim Laboratory of Complex Cyber Physical Systems in ENSAM, Hassan 2 University, Casablanca, Morocco Laboratory of Electrical Systems & Control Engineering at Aïn Chock Science facultyHassan 2 University, Casablanca, Morocco Laboratory of Mathematics, Informatics in Engineering Science in Science & Technical faculty, Hassan 1 University, Settat, Morocco


INTRODUCTION
The exceptional growth of the photovoltaic systems market is obviously due to major technological innovations and lower costs for photovoltaic panels. It is also due to major research efforts in semiconductor switch design and technological advances in power electronics and digital electronics [1]. Static converters have become much more efficient, reliable, and compact. Their function is also gradually improving, and their field of application is expanding. In this context, many multilevel inverter topologies have been investigated and developed to replace the two-level inverters in various medium and high voltage applications requiring increased performance: energy, grid-tie renewable energy systems, high voltage direct current (HVDC) power transmission, electric vehicles, and a multitude of industrial applications [2]. Furthermore, the continuous and constant development of power electronics and the increasing progress of fully controlled semiconductor technology presents cost-effective opportunities for the design and implementation of several interesting architectures and topologies of multilevel converters. In both academia and industry, these topologies are prevalent as power electronic interfaces due to their outstanding characteristics such as: lower switching power loss as a result of lower switching frequency and reduced device voltage, reduced voltage stress (dv/dt), lower THD, and harmonic contents, and reduced output filter size and cost [3], [4]. Splitting the voltage across the switches also allows for the use of reduced voltage rating semiconductors that have optimized dynamic performance and are economical because they are massproduced [5]- [7].
The conventional multilevel inverter topologies mostly applied in grid-tie renewable energy and industrial applications include the Neutral Point Clamped (NPC) type shown in Figure 1 (a), the Flying Capacitors (FC) type in Figure 1 (b), the Cascaded H-Bridge converters (CHB) type with separate and isolated DC sources as shown in Figure 1 (c), and Modular Multilevel Converters depicted in Figure 1 (d) [8]- [11]. However, the multilevel converters consist of several drives, a lot of active power switches, and bulky passive power components which lead to considerable cost and increased size of the device; as matter of fact, the number of semiconductor power switches (NS), drivers and passive components required for achieving these topologies increases with the number of desired levels (NL) and the complexity of their structure is thereby increased: NS =2*(NL-1).
The NPC multilevel converters use, in addition to active switches, a large number of clamping diodes for a high number of voltage levels causing more conduction losses and generating reverse recovery currents that affect the switching power loss of the overall system [12]. In the FC multilevel inverters, the increased number of high voltage capacitors leads to bulky equipment, high cost, and complex control methods to balance the voltages of both flying and DC-link capacitors. To overcome these constraints, researchers and authors investigated and proposed many hybrid topologies: Active Neutral Point Clamped type that combines NPC and FC structures. The authors of [12] propose a 7S-5L-ANPC topology with only 7 actives switches by leg: one interrupter and ten clamping diodes less than the NPC structure. In [13], the researchers upgrade the structure of 8S-5L-ANPC to an interesting 10S-9L-MANPC topology by adding a two-level converter leg, but they still use a flying capacitor. In [14], one proposes a new topology of a 9-Level Voltage Inverter using only 9 active power switches. The CHB topology includes the series connection of several H-bridges. It is applied for various applications due to its simplified model that can be categorized into symmetrical and asymmetrical topologies. The use of asymmetric CHB structures allows the further increase of the number of levels therefore the quality of the output signals without increasing the switch number [15]. The series connection of two H-Bridges with asymmetries ratio 1:3 can produce 9 voltage levels using only 8 switches instead of 16. The authors of [16] implement an interesting 27-level inverter using three cascaded H-Bridge (12 switches) with asymmetries ratio 1:3:9.
The main objective of this paper is to propose an improved topology of the Multilevel Inverter, based on two cascaded asymmetrical stages that significantly decrease the number of active power switches and reduce the Switching losses which are directly linked to the frequency PWM operation. Based on this, a novel topology of a 25-Level inverter is developed. Our proposed topology generates a staircase output voltage waveform with 25 levels using only ten switches, much less than forty-eight, the number of active switches used in the equivalent conventional topology, and without an excessive number of clamping diodes or flying capacitors used in NPC, FC, or Hybrid structures. The reduced costs, volume, and control complexity in this novel solution will certainly lead to its adoption in a large range of voltage levels photovoltaic systems. The active elements of this solution can be distributed in such a way that each stage can be connected to a different photovoltaic string. However, the control and the modulation strategy that must be developed will be very elaborate and complicated.
The rest of the paper is organized as: Section 2 presents the operating principle of the ten-switch 25level proposed topology based on two cascaded asymmetric T-Bridges. A deep comparison between our multilevel inverter and other topologies (NPC, FC, CHB, MMC, ANPC) in terms of the number of required components, system volume, device voltage stress, and efficiency is also developed. In Section 3, we detail the multilevel control strategy which consists of a Modified Hybrid Multilevel Pulse Width Modulation Method (MHMPWM) elaborate for controlling our asymmetrical Cascaded T-Bridges. At the end of this section, we propose the block diagram of the proposed MHMPWM circuit controlling the ten active semiconductor switches. In Section 4, the verification and simulation results are reported in two cases: with and without PWM Control. The different illustrations justify the correct operation and the good performance of our complete multilevel solution. Finally, this paper is concluded in Section 5.

OPERATING PRINCIPLES OF THE PROPOSED 25-LEVEL CASCADED T-BRIDGE VOLTAGE INVERTER 2.1. New multilevel structure design from basic submodules
During the last few years, in their investigation and search for better solutions, several authors have worked on topologies derived from conventional structures [17]- [19] others on modular structures by assembling several basic units depends on the desired output signal quality and the voltage rating of the semiconductor power switches. Each of these multilevels solutions has benefits and limitations and can be classified into two categories: Topologies with inherent negative voltage levels and topologies with negative voltage levels by H-bridge [20], [21].
In Power Electronics, the basic submodule half-bridge structure (SM1) shown in Figure 2 (a), has two modes and provides two voltage levels (V DC or 0) at output terminals (a, c). In Figure 2 (b), the H-bridge basic module (SM2) is developed by combining two submodules (SM1) in parallel and operates one DC source. SM2 can generate three voltage levels (V DC , 0, -V DC ) at the output terminals (a, b). The combination of two submodules (SM1) mounted in antiparallel, allows the creation of the T-type derived submodule (SM3) shown in Figure 2 (c). The T-type structure generates three unipolar voltage levels (0, V DC , 2V DC ) at terminals (a, b). The parallel connection of submodules SM1 and SM3 makes these voltages bipolar and leads to the creation of the T-Bridge structure as depicted in Figure 3. The T-Bridge is then considered as a 5level inverter structure that can generate (2 V DC , V DC , 0, -V DC , 2V DC ). In this operation, the T-Bridge uses only five active switches instead of eight and more other components like clamping diodes, flying capacitors, and isolated DC sources in classical topologies. In this structure, we are in a configuration where NS=N L more less than 2(N L -1) [21]. The authors of [22] propose an interesting 31-level structure with only 14 switches and 4 asymmetric DC sources.
In the T-Bridge topology, the five power switches have different voltage stress: S 1 , S 2 , S 3 , and S 4 need to block unipolar voltage 2V DC whereas the switch S 5 needs to block the bipolar voltage V DC and -V DC . Therefore, to significantly increase the number of voltage levels and remarkably reduce the switches and components count, we develop a new topology of a 25-Level inverter based on two cascaded asymmetrical T-Bridges using only ten switches as depicted in Figure 3.

Basic operating principle of 10S-25L voltage inverter
The proposed topology is composed of two cascaded asymmetric sub-circuits using four DC supplies. Each sub-circuit is a T-bridge consisting of two basic units: T-type (SM3) and Half-bridge (SM1) submodules. Each T-bridge stage generates five voltage levels. By combining the possibilities of each stage, our multilevel inverter can provide up to 25 voltage levels. Table 1 and Figure 4 illustrate the switches states for many output voltages levels. The concept of this structure can be simply extended to obtain more voltage levels by adding more cascading T-bridges.
A careful analysis of the Table 1 shows that the choice of the VDCi values is very important and must allow the following criteria: i) the output voltage must be symmetrical with respect to zero; ii) the values of the zones A, B, C, D, and E must not overlap; iii) the step between the different values must be constant. For this purpose, we deduce the essential relationships between the different V DCi voltages: As depicted in Figure 5, the proposed topology then becomes a cascade of two Asymmetric T-bridge stages: i) a Low Voltage stage generating at its terminals the five levels (-2V DC , -V DC , 0, V DC , 2V DC ); and ii) a High Voltage stage also generating five levels (-10V DC , -5V DC , 0, 5V DC , 10V DC ). Table 2 shows the states of the HV and LV stage switches for output voltage values ranging from -12V DC to +12V DC .

Comparison between our 10S-25L voltage inverter and conventional multilevel topologies
It is important to compare the proposed 10S-25L Voltage Inverter to other equivalent structures in order to illustrate its advantages and strengths. The proposed multilevel inverter synthesizes 25 voltage levels at the output terminals using only ten active switches. In parallel, up to 48 active switches and more other components are needed in classical topologies. The comparison of this 25-level inverter with other existing nine-level topologies is summarized in Table 3. The comparative analysis clearly shows that our 10-Switch 25-Level inverter topology is more interesting in terms of THD and it is less bulky and uses fewer electronic components and devices than many other recent and conventional topologies. However, it is noticeable that in this topology, the switches need to withstand different voltage stress: − Switches S 1 , S 2 , S 3 , and S 4 must be able to block a unipolar voltage equal to 2V DC ; − Switches S' 1 , S' 2 , S' 3 , and S' 4 must be able to block a unipolar voltage equal to 10V DC ; − S 5 must withstand a bipolar voltage of V DC and -V DC ; − S' 5 must withstand a bipolar voltage of 5V DC and -5V DC .

PROPOSED MODIFIED HYBRID MULTILEVEL PWM CONTROL STRATEGY
Many publications and studies are presenting several modulation methods designed to improve harmonic characteristics, control dynamics, filter size, and switching loss. The multi-carrier-based sinusoidal pulse-width modulation (MSPWM) scheme is one of the most used modulation methods for multilevel structures [23], [24]. One distinguishes two conventional categories: Level-shifted PWM (LS-PWM) and Phase-shifted PWM (PS-PWM). However, it should be noted that each special structure requires a dedicated control and modulation method. Thus, for this singular multilevel topology, special multilevel modulation control is needed and must be developed. As depicted in Figure 5, our 10S-25L Voltage Inverter is composed of two cascaded T-Bridges with asymmetric DC source ratio 1:5. The 25 voltage levels are obtained by merging each of the five combinations of the HV stage with the five combinations of the LV stage. The switching states and their corresponding voltage level are depicted in Table 2 making the operation and level generation process much more comprehensible. We first note 5 zones A, B, C, D, and E associated with the HV stage levels: 10V DC , 5V DC , 0, -5V DC , and -10V DC . It is observed that the states of the LV stage switches are redundant and do not depend on these zones but on the deviation of the output voltage from the voltage levels (V ab -5nV DC ). The voltages delivered by the LV stage, whatever the zone, are: 2V DC , V DC , 0, -V DC , -2V DC . So, the Multistep Modified Reference Voltage allowing the control of the LV stage will have the following recurrent expression: with The switches S 3 and S 4 are clamping to a high or low state depending on the sign of the modified modulating reference signal V M2REF : the switch S 4 is ON when V M2REF is positive and S 3 is in a high state in the opposite case. The unipolar modified modulating reference signal V UM2REF depicted in Figure 6 is compared to two triangular carrier bands, which are level-shifted incrementally by 1with the same amplitude 1 in order to generate the PWM commands for the three power semiconductors (S 1 , S 2 , S 5 ).

RESULTS AND DISCUSSION
In this section, a single-phase 10-switch 25-level voltage inverter with an output L-filter is modeled using MATLAB/Simulink. To evaluate the performance of our multilevel inverter, we test it with non-high switching frequency further reduce the switching power losses in semiconductors components. Our goal is to generate a sinusoidal voltage with amplitude and frequency fixed by the reference signal with improved harmonics characteristics (THD), minimum switching loss and minimum cost and size of L-filter at the system output. Table 4 summarizes the considered simulation parameters for the multilevel voltage system. In this section, the obtained simulated results are discussed. It is intended to confirm the good performance of our multilevel inverter with its elaborate control. It is then easy to demonstrate that the objectives of this work are fully achieved. Figure 7 shows the synthesis of the signals allowing the PWM control during all the phases and zones of the sine reference signal evolution in detail. Figure 8 (a) shows that, even without PWM control, the output voltage delivered by the inverter is a perfectly sinusoidal stepped signal of 25 levels. Its harmonic distortion rate is 3.27% as depicted in Figure 8 Figure 9 shows the inverter output signals when the MHMPWM control is operated. As depicted in Figure 9 (a), the inverter output voltage waveform shows that our Cascaded asymmetrical structure with Modified Hybrid Multilevel PWM command worked well: we have 25 voltage levels perfectly modulated in time according to the sine reference voltage. PWM switching takes place for the most part in the LV stage, thus minimizing the harmonic distortion rates: THD_ VAB =5.39% as shown in Figure 9 (b), THD_ IS =THD_ VR =082% in Figures 9 (d) and (f). Subsequently the switching losses are minimizing. Figures  9 (c) and (e) also illustrate respectively that the voltage V R and current I S at the output of the L-filter are quasi sinusoidal. After modeling the entire system as shown in Figure 5, this power multilevel converter can be controlled by a linear or nonlinear regulator (PID, backstepping, sliding mode…) to ensure good performance with respect to disturbances [25]. (f) its harmonic spectrum.

CONCLUSION
In this paper, a novel 25-Level inverter topology has been proposed with many benefits and features: very reduced count part, highly sinusoidal output signals with low harmonic content and reduced commutation losses. As depicted in the comparison with the other inverter's topologies, it requires only TEN active switches for a single-phase converter. The design of this cascaded asymmetric structure from basic submodules has been developed and detailed. The operating principles and switching states are presented. A detailed comparison between the proposed and the conventional topologies in terms of the number of switches, system volume, voltage stress, and switching loss is made. The development of a specific modulation strategy of the 10S-25L VI has been proposed. It consists of a modified hybrid multilevel PWM method essentially based on a unipolar multistep modified reference control signal and with outputs decoding operating areas. According to simulation results, the validity and advantages of the proposed topology and modulation method are demonstrated. Therefore, the proposed 25-Level inverter is a suitable and improved solution that can be used in E-mobility and grid-tie PV systems applications. Elhassane Abdelmounim received his PhD in applied Spectral analysis from Limoges University at science and technical Faculty, France in 1994. in 1996, he joined, as Professor, applied physics department of science and technical faculty, Hassan 1 st University, Settat, Morocco. His current research interests include digital signal processing and machine learning. He is currently coordinator of a Bachelor of Science in electrical engineering and researcher in "ASTI" System Analysis and Information Technology Laboratory at science and technical faculty, Hassan 1st University, Settat, Morocco.