A proposed asymmetrical configuration of cascaded multilevel inverter topology for high level generation

Received Jul 2, 2021 Revised Jan 17, 2022 Accepted Jan 25, 2022 Multilevel inverters are having high demand in high power applications. It works in medium voltage range. In this converter, for specific time intervals fewer switches will be conducting so switching loss is also reduced. This paper represents overall total harmonic distortion (THD) for different levels and different carrier frequencies. Switching loss, conduction loss of inverter has been discussed and hence inverter efficiency can be calculated. Phase displacement pulse width modulation method has been proposed in order to generate pulses. The proposed topology is well presented by its practical implementation with two current direct sources. All the simulations are being carried out using MATLAB/Simulink platform to validate the hardware results.


INTRODUCTION
Multilevel inverters are highly in demand in high power and medium voltage applications [1]. There are mainly three different types of multilevel inverters are being focused for industrial applications. Various topologies had been developed since 1970. It can be interfaced to renewable sources i.e., solar photo voltaic, wind and fuel gas [2]− [4]. Considering the number of components, high reliability cascaded multi level inverter (MLI) is being chosen. As the number of level increases, the number of H-bridges also increases [5], [6]. This makes the system more complicated. By increasing the number of levels in the inverter, the output voltages have more steps generating a staircase waveform, which has a reduced harmonic distortion. Depending upon the voltages sources cascaded MLI are classified into two, i.e. symmetrical and asymmetrical Cascaded MLI [7]. Direct voltages are having different values in asymmetrical Cascaded multilevel inverter [8]. So, the Inverter achieves higher number of voltage levels compared with symmetrical configuration for same number of level generation [9], [10]. Several newly developed MLI topologies, popularly known as "reduced device count (RDC)," have been reported in recent years [11]− [15]. In this paper a novel topology has been proposed and its asymmetrical configuration has been emphasized to produce more number of levels. As the number of levels increased the output waveforms become more sinusoidal in nature. Hence total harmonic distortion (THD) reduces. Phase-shifted and level-shifted are the two modulation schemes using carrier based pulse width modulation (PWM). Using the same frequency modulation index in the different modulation techniques, the equivalent switching frequency in the level shifted technique is significantly lower than in the phased shifted method [16]− [21]. This turns into a better

RESEARCH METHODOLOGY 2.1. Existing topology
The existing topology as shown in Figure 1 has two voltage sourcesV1 and V2. It has two capacitors C1 and C2connected to one voltage source side i.e., V1and seven switches. If the values of V1 and V2 are equal it is treated asymmetrical configuration. It can produce up to 11 levels with certain voltage combination. Hence to generate higher levels a new modified topology has been proposed in Figure 2.

Proposed topology
The existing topology has been modified and represented in Figure 2 in order to generate higher levels. As the proposed topology also generates same levels of output voltage and current waveforms in symmetrical configuration of existing topology, its asymmetrical configuration has been highlighted and presented in this section. It has two voltage sources i.e.V1 and V2 and four capacitors i.e.C1-C4 connected as shown in Figure 2. It has six unit directional i.e., S1, S2, S3, S4, S7, and S8 and two bidirectional switches i.e., S5 and S8 in the circuit.

MODES OF OPERATION
In this section different modes of operation of the proposed converter for thirteen level generation have been represented from mode 1 to mode 13 order to generate first level i.e., Vdc, S5, S2 and S8 are conducting. Similarly, to generate second level, in mode 2 operation, S6, S4, and S8 are turned on keeping capacitor C2 charged. In mode 3 operation, C2 discharged by charging capacitor C1.In order to generate all the six positive levels, the lower switch i.e., S8 is being turned on and to generate all the six negative levels, switch S7 has been turned on in the Figure 2. Similarly, S1, S7, S3, or S2, S4, and S8 are turned ON, short circuiting the load, to generate zero level respectively.

SWICHING STATES
This section represents various switching states of the proposed topology. It shows V 1 =V/2, V 2 =V where V dc =V/4 which is known as unsymmetrical binary configuration, to generate 13 level sand V 1 =V, V 2 =3 V where V dc =V/2, which is called as unsymmetrical trinary configuration, to generate 17 levels respectively. Figure 3 depicts to generate first level i.e., Vdc in thirteen level generations Switches S5, S2, S8 are conducting. To generate second level i.e., 2Vdc in thirteen level generations switches S6, S4, S8 are conducting. Similarly, six positive levels are generated and six negative levels are generated along with zero level as represented in different modes of operation in Figure 3 (see Appendix). Table 1 explains the different switching strategies of the proposed converter. It also depicts about the switches and diodes are conducting for particular level generation.

SIMULATION RESULT ANALYSIS
Various types of the pulse width modulation (PWM) techniques are existing out of which level shifted PWM technique is being considered because of its many advantages over other conventional techniques. Figure 4 depicts the simulation diagram of the proposed converter at carrier frequency 10 KHz and modulation index at 1. S5 and S6 are two bidirectional switches and S1, S2, S3, S4, S7, S8 are unidirectional switches in Figure 2. Figure 4 represents load voltage and load current wave form at carrier frequency = 10 KHz. Simulation has been carried out for R=10 Ω, L=25 mH at modulation index 1. Figure 4 (a) indicates output load voltage for 13 level. Average output voltage is 43.85 V at THD=5.44%. The fundamental cycle has been represented in voltage waveform which is from 0 to 0.02 sec. Voltage THD also within IEEE standard. Six positive levels, six negative levels of unequal voltage distribution represented in Figure 4 (a) which shows the asymmetric nature of the proposed multilevel inverter. Figure 4 (b) indicates output load current for 13 level. Average output load current is 3.45 A at THD = 0.28%. Current THD is also within IEEE standard.
Fundamental cycle has been represented in voltage waveform which is from 0 to 0.02 sec. Figure 4 (c) indicates average output voltage is 38.85 V with THD=3.9%. Figure 4 (d) indicates average output current is 3.5A with THD=1.7%. Voltage THD also within IEEE standard. Eight positive levels, eight negative levels of unequal voltage distribution along with zero level represented in Figure 4 (c) which shows the asymmetric nature of the proposed multilevel inverter. Figure 4 (d) indicates output load current for 17 level. Average output load current is 3.5 A at THD=1.7%. Current THD is also within IEEE standard. Figures 4 (a) and 4 (b) also depict with increase in level generation of the same converter THD is reduced. Table 2 depicts various losses occurred across the semiconductor switches i.e., at 10 KHz carrier frequency. Table 2 also describes that conduction loss across the switches is same where, as switching loss depends on the usability of the switch. Switches S7 and S8 are mostly used when the converter is working to generate positive levels and negative levels respectively. Hence switching losses are more in S7 and S8 compared to other switches. Table 3 depicts about the inverter loss. According to the various researchers [22]− [25] an inverter has major two types of losses i.e., switching loss which occurs when a switch is conducted (turn on) and also when it is in off state (turn off), conduction loss when the switch is in conduction state. It has been calculated from its input power and output power with its voltage THDs and current THDs. Table 3 Table 4 depicts voltage THD is reduced and current THD is increased with increase in modulation index. Hence it is always advised to operate the converter at high carrier frequency and at modulation index 1. At 10 KHz carrier frequency voltage THD and current THD are found to be minimum at modulation index 1. Figure 5 represents current THD at various carrier frequencies of the inverter. Current THD has been reduced as the carrier frequency increases. It indicates that current becomes more sinusoidal at higher carrier With high modulation index voltage THD reduces which has been observed in Figure 6. Hence it was advised to operate the inverter at modulation index 1 in order to make the inverter output more distortion free. Also, in Table 4 it was mentioned clearly.  Figure 5. Current THD vs carrier frequency Figure 6. Voltage THD vs modulation index at 10 KHz

HARDWARE REALIZATION
To verify the effectiveness of the proposed topology, experimental results have been presented in this section. In Figure 7 the entire converter has been considered as a system/Plant to which two sources are attached. The output of the inverter is PWM controlled and it is controlling the system operation. The block diagram of hardware which has been designed in research lab-III of Kalinga Institute of Industrial Technology deemed to be university (KIIT). Circuit is designed using EAGLE software. They are fed to gate driver circuits. Gate driver circuits have input supply from 230/15 V, 1A step down transformer. Pulses generated from driver circuits have been fed to each MOSFET IRF540 N gate terminals. Output of the power circuit is given to the load RL type RO2. Power supply of MOSFET gate driver circuit 3. Gate drive circuit 4. Main power circuit 5. Output connector from DSPACE. Figure 8 explains the hardware diagram of the proposed converter where input power supplies are through MOSFET gate driver circuits. MOSFET IRF540 Ns are taken as switches. Six MOSFETS work with six gate driver circuits. DSPACE has been connected to output waveforms in order to describe the turn off and on state of the inverter.

CONCLUSION
In this research article, the detailed analysis of the proposed asymmetrical cascaded multi level inverter has been carried out successfully at different modulation index and carrier frequencies. The output waveforms are more sinusoidal and hence better power quality can be obtained at higher carrier frequencies.
The proposed topology has been fabricated and verified with its simulation result also. Input voltage of 15 V and output voltage is 14 V which is quite high compared to other existe topologies as cited in the references. Also THDs if the proposed topology are nominal.

Lipika Nanda
is working as an assistant professor since 2007 in KIIT University.Her broad working area is design of power converters, multi-level inverter and its applications. She is a life member of various professional societies like SESI, ISTE, ISLE, ISCA, and IEEE. She has 3 Australian patents, 2 book chapters. She has published around 20 papers in international journals and conferences. She can be contacted at email: lnandafel@kiit.ac.in.

Chitralekha Jena
had joined in KIIT University as an assistant professor since 2012.She had completed her PhD from Jadavpur University in the year of 2017. Her research area includes optimization of different power system problems, load frequency control, renewable energy, and power management of micro grid. She has more than 20 publications in reputed journals and conferences. She can be contacted at email: Chitralekha.jenafel@kiit.ac.in.

Arjyadhara Pradhan
is working as an assistant professor since 2009 in KIIT University. Her area of interest is Power Electronics, Electrical Drives, and Renewable Energy Systems. She has 8 Australian patents and 2 Indian patents. She has published around 20 papers in international journals and conferences. She can be contacted at email: arjyadhara.pradhanfel@kiit.ac.in.

Babita Panda
has fifteen years of experience in education. She is working as an assistant professor in KIIT University. Her area of interest is Power Electronics, Electrical Drives, Renewable Energy Systems and Control System. She has more than 25 publications in reputed journals and conferences. She can be contacted at email: babitapfel@kiit.ac.in.