A family of switched-impedance network enhanced-boost quasi- Z-source inverters

Received Oct 13, 2020 Revised Jan 19, 2022 Accepted Jan 25, 2022 This paper proposes a family of novel enhanced-boost quasi-Z-source inverters (EB-qZSIs). For the similar input voltage and shoot-through duty ratio, similar to that of enhanced-boost Z-source inverter/enhanced-boost qZSIs, the presented topologies provide very high voltage boost at high modulation index with improved quality output waveform. Compared to EBZSI and EB-qZSIs, these topologies provide less capacitors stress, which reduce the volume and cost of the system. Akin to traditional EB-qZSIs, the presented novel impedance networks share joint ground with the source and inverter bridge, also reduces the initial inrush current. Among the four types of proposed configurations, the type-1 of discontinuous input current (DIC) EB-qZSIs offers fewer stress athwart the capacitors and little inrush current at start-up condition. Consequently, type-1 is considered and illustrated for the examination, simulation, and hardware execution. The steady-state operation and derivation of boost factor, peak direct current-link (DC-link) voltage and capacitor voltages are derived for both continuous conduction mode (CCM) and discontinuous conduction modes (DCM). The Z-network elements design, and evaluation with other Z-networks are also carried out. Lastly, the hypothetical investigation is confirmed with simulation and experimental tests.


INTRODUCTION
Single-stage voltage source inverter (VSI) and current source inverter (CSI) can only offer either step-down or step-up direct current-alternating current (DC-AC) conversion correspondingly [1]. To achieve high output voltage, an additional boost converter has been cascaded among the source and the inverter bridge, or a step-up transformer has to be connected at the output side of the inverter bridge. This two-stage conversion rises the complexity and cost of the system and lowers the efficiency [2]. Besides, the ON state of both the switching devices in any phase leg of both the single-stage and two-stage converter can lead to deadshort circuit of the input supply. To avoid this, an extra dead-band circuit is needed between the phase legs, which increases the cost and distortion in the output waveform. Therefore, to avoid the above-mentioned drawbacks and to have greater ac output voltage with high reliability, a single-stage Z impedance-source inverter (ZSI) was proposed, which consist of two capacitors, two inductors and the input diode in the Z-network [3]. The traditional ZSI has some problems; those difficulties can be eliminated by some adjustments in the Z-network with same count of elements [4], [5]. Nevertheless, these networks could'nt expand their voltage gain. Consequently, to expand the voltage gain, the inductors in traditional ZSI were swapped with switched-inductor (SL) cells [6]. The downsides of SL-ZSI were minimized in [7]. The protracted quasi(q)-ZSIs were projected in [8] with higher voltage gain and slighter quantity of inductors and diodes. Pan [9], L-ZSI was presented to prohibit the inrush current with only inductors and diodes in the impedance network. The switched-boost inverters (SBIs) which were proposed in [10]− [14] offers about matching voltage gain as that of the ZSI [3] with a reduced quantity of inactive elements but with an additional set of diode and switch.
To further enhance the boost factor by changing together duty cycle and turns ratio easily, numerous magnetically-coupled Z-source (MCIS) configurations were presented in [15]− [21]. Depending on the components used in the impedance network, these MCIS networks can be classified as two winding [16], [17], three winding [18], [19], and active MCIS networks [20], [21]. But either their magnetic coupling must be robust or their leakage inductance must be small enough. Then, massive voltage prickles will appear athwart the dc-link which requires higher voltage rating switching devices, which in turn rises the cost [22].
Consequently, enhanced-boost ZSI (EB-ZSI) was presented, which provides high voltage gain at low duty cycle [23]. Akin to traditional ZSI, the EB-ZSI has certain downsides; such as discrete input current, does not share joint ground with supply, hefty inrush current, and high capacitor stress. Some of these difficulties are eradicated by EB-qZSIs using equal count of elements in the Z-network [24], [25]. The two arrangements of EB-qZSIs are revealed in Figure 1 [25]. In Figure 1 (a), capacitor C2 negative terminal is connected to positive terminal of capacitor C3 where as in Figure 1 (b) it is connected to supply positive terminal. The boost factor of EB-ZSI [23] and EB-qZSIs [24], [25] are identical and is given as shown in (1).
Where B-boost factor, D0-shoot-through duty ratio, V^PN-peak dc-link voltage, and VDC-input voltage.  This paper presents the four novel arrangements of discontinuous input current (DIC) EB-qZSIs with same number of components as that of EB-ZSI/qZSIs, but with low rating due to less capacitor stresses and low starting inrush current. Section 2 describes the working principles, derivation of boost factor and capacitor stresses of type-1 DIC EB-qZSIs for both continuous conduction mode (CCM) and discontinuous conduction mode (DCM). Design of Z-network elements are carried out in section 3. In section 4, the evaluation of current Z-network configurations and the projected configurations are made. Lastly, to confirm the hypothetical examination, the simulation and experimental tests are carried out in section 5.

PROPOSED TOPOLOGIES CIRCUIT ARRANGEMENTS AND WORKING PRINCIPLES
The two arrangements of EB-qZSIs operating in continuous input current (CIC) mode are shown in Figure 1 [25] and the four proposed circuit arrangements of the DIC EB-qZSIs topologies are revealed in Figure 2. In Figure 2 (a), the capacitors C1, C2, and C3 are connectected in series due to which it results in less stress across them. The capacitor C1 negative terminal is connected to negative terminal of C3 instead of positive terminal and can be depicted in Figure 2 (b). In Figure 2 (c), the capacitors C1, C2, and C3 negative terminals are connected to supply positive terminal, which results in increased voltage stress across them. Figure 2 (d) is similar to Figure 2 (b) except, capacitor C2 negative terminal is connected to capacitor C3 positive terminal instead of capacitor C1. The elements (i.e., both active and inactive) used in these projected configurations are identical as that of the EB-ZSI [23]/EB-qZSIs [24], [25] (i.e., the impedance network is having five diodes, four capacitors, and four inductors). During zero states, these proposed topologies draw discontinuous input current from the supply with reduced capacitors stress. This discontinuous input current can be avoided using the maximum boost control modulation technique in which all the zero states are converted to shoot-through states [26]. Likewise, these configurations lessen the starting inrush current problem. Akin to traditional EB-qZSIs [24], [25], the presented topologies share common ground with the source and inverter bridge, reduces the capacitors stress, and lessens staring inrush current. All these presented configurations can be controlled using the modulation methods presented for the conventional ZSI [3], [26], [27]. In this framework, the simple boost method (SBC) [3] is used for the examination, comparison, simulation and hardware tests. The principle of operation for the presented topologies is identical to that of the traditional ZSI, having both shoot-through and non-shoot-though states. As all the presented four topologies of DIC EB-qZSIs have the same characteristics, therefore type-1 of DIC EB-qZSI is considered as an example for analysis purpose.  Figure 2 (a) depicts the illustration of presented type-1 DIC EB-qZSI in which the capacitors C1, C2, and C3 are connected in series to share the dc-link voltage which inturn results in the less stress across them. − Shoot-through state:

Operation and discussion in continuous conduction mode
The illustration of the presented topology for type-1 during shoot-through state is depicted in Figure 3 (a). Throughout this mode, both the switching components of either any one-phase or any twophases or all the three-phase legs are turned-on at the same time to boost the voltage to a required level. The diodes Din, D1, and D2 are OFF, whereas the diodes D3 and D4 are ON. All the inductors are charged by the input supply and the capacitors, and these inductors store the energy.
According to Kirchhoff's voltage law (KVL), the voltage across inductors and diodes can be stated as: and the input energy is shifted to the dc-link to increase the voltage. The capacitors are charged from the input supply and energy is stored. The resulting expressions can be found subsequently applying KVL to Figure 3 (b).
After applying the volt-sec balance principle to the inductors (i.e., L1, L2, L3, and L4), the capacitor voltages can be obtained as: The expression for the peak dc-link voltage can be written as: From the terms (1) and (7), it can be detected that the boost factor, B of the projected configuration for type-1 is same to that of the topologies proposed in [23], [24]. In a similar way, the boost factor for the remaining three topologies can also be obatained and it will be identical as that of EB-ZSI/qZSIs. Similarly, it can be derived that the average dc-link voltage across the inverter bridge of all the four projected topologies is identical to the EB-ZSI [23]/EB-qZSIs [24] and is expressed as: The peak-phase output voltage is expressed as: The overall ideal voltage gain G of the presented network configurations in terms of modulation index M can be well-defined by: Voltage gain, = . = 2 2 −1 (10)

Operation and discussion in continuous conduction mode
The converter may operate in DCM because of low switching frequency, light loads, and low inductance values of inductors [21], [28]. The DCM operation mode causes over-boosting of dc link and output voltage, which can lead to instabilities of the converter and must be taken in consideration while deciding components and switches. Figures 4 (a) and 4 (b) depicts the typical current and voltage waveforms of type-1 DIC EB-qZSI operating in CCM and DCM respectively.  The functioning period of DCM consists of an active state tA, a shoot-through state t0 and a discontinuous conduction state t2: The above equation could also be represented as: where DA-duty cycle of active state, D0-shoot-through state, and D2-discontinuous conduction state. Whereas the equivalent configurations of the EB-qZSI converter working in the shoot-through and active states remain the identical as in Figure 3. When the converter is in a discontinuous conduction mode (DCM) t2, the voltages of the inductors L1, L2, L3, and L4 are equal to zero. For a discontinuous conduction mode, in (2) and (4) could be extended as shown in: Similarly, for inductors L3 and L4, it can be expressed as: From the above equations, we can obtain capacitor C3 and C2 voltages as: From above two equations, it can be obtained capacitor C4 and C1 voltages as: The ideal DC-link voltage of DIC EB-qZSI for the DCM can be expressed as: where, BDCM (i.e., boost facror during DCM) is written as: Comparing (7) and (20) it can be specified that the changeover from CCM to DCM rises the boost factor. This is so called over boost effect, which can lead to unbalanced operation and damage of elements. It can also be detected that, at D2=0; the boost factor expressed in (20) is same as (7). Similarly, the capacitor voltages expressed in (17)- (19) are same as (6) at D2 = 0.

PARAMETER DESIGN OF Z-NETWORK
Normally, the design of Z-network elemenys primarily depends upon the component current and voltage stresses which are summarized in Table 1. Similarly, in this section type-1 DIC EB-qZSI is taken as an illustration to exemplify the components design. As enlightened in section 2, in shoot-through state, the capacitors charge the inductors, and it is also detected that the inductor voltages (VL1=VL2 and VL3=VL4) are same for all proposed topologies and the arrangements proposed in [23], [24]. EB-qZSI [24] Continuous input current (CIC) Family of proposed configurations of EB-qZSIs Discontinuous input current (DIC) configurations Figure 1 where fs -the switching frequency, ksh -the no. of shoot-through states over a period, T, and Δ -denotes the inductor current and capacitor voltage ripples. From above equations, it can also be observed that the components (capacitors, inductors) ratings can be reduced with increase in switching frequency. For a lossless system, the input and output power of the converter must be in balance (i.e., Pin = P0), where, Pininput power and P0is the output power. In order to operate the inverter in CCM, the minimum inductor current ( _ ) should be greater than zero. The average inductor current should be equal to the peak value of the phase current ( ). Exactly, it is written as: substituting the (21) and (23) where load impedance per phase, = + , and -resistive load per phase, -inductive load per phase, øload power factor, and fsswitching frequency.

ASSESSMENT OF THE PROPOSED DIC EB-qZSI TOPOLOGIES
In this segment, the projected four configurations are related with supplementary Z-source networks, such as the SL-ZSI [6], EB-ZSI [23], and the EB-qZSIs [24], [25]. The expressions of boost factor, components voltage, current stresses, and the input current are derived and are summarized in Table 1. The diodes voltage of the projected configurations and the EB-ZSI/EB-qZSIs is equal and is fewer than the SL-ZSI. Likewise, for comparison purpose, the number of components used, start-up current, and the sharing of common ground are briefed in Table 2. The assessments are accomplished on their boost abilities and components stresses.   Figure 5 portrays the assessment of boost factor and stress across the power switches for the traditional ZSI, SL-ZSI, EB-ZSI, EB-qZSIs, and the projected configurations. As shown in Figure 5  the similar duty ratio D0, the boost factor of the projected configurations is identical as to that of the EB-ZSI/ EB-qZSIs and is stronger than the ZSI and SL-ZSI. Correspondingly, the plot of switch stress versus voltage gain G for the projected configurations and the ZSI, SL-ZSI, EB-ZSI, and EB-qZSIs are shown in Figure 5 (b). From this figure it is detected that the stress across the switch in the projected configurations are same as that of the EB-ZSI/EB-qZSIs and is less when compared to ZSI, and SL-ZSI. Hence, lesser rating active devices can be used which decreases the cost.

Boost factor and switch stress assessment
(a) (b) Figure 5. Evaluation of (a) boost factor and (b) switch stress

Comparison of capacitor stress
As compared in Table 1, Figure 6 shows a conspiracy of the capacitor's stress versus voltage gain for all the four projected configurations, SL-ZSI, EB-ZSI, and the EB-qZSIs. It is observed from Figure 6 (a) and Figure 6 (b), that the stress across capacitor C1 and capacitor C2 is less in the proposed topologies. Figure 6 (c) shows that stress across the capacitor C3 is same in the proposed topologies as that of EB-qZSIs [24]. From this illustrattion, it can be detected that the total stress across the capacitors is less in the projected configurations when compared to other configurations. Furthermore, it is also detected that the capacitor's stress and starting inrush current in case of type-1 DIC EB-qZSI is less when compared to other three proposed configurations.

DISCUSSION ON SIMULATION AND EXPERIMENTAL RESULTS
To authenticate the hypothetical investigation discussed in section 3, the simulation and experimental test is performed. In order to harvest 110 Vrms as the output voltage, the projected converter is operated with simple boost control technique [3] at VDC = 60 V, D0 = 0.24112, M = 0.75888, with L1,2,3,4 = 1 mH, C1,2,3,4 = 1000 µF, load per phase is Rl = 40 Ω, Ll = 2.5 mH, and switching frequency, fs =10 kHz. For a given input voltage and duty ratio, all the four proposed arrangements will offer identical DC-link voltage and are obtained as 396.3 V peak theoretically. Similarly, the theoretical values of boost factor B and voltage gain G are obtained as 6.6 and 5 respectively.

Simulation results
The simulations of capacitor voltages along with input current are depicted in Figure 7 for all the four presented topologies. It is also detected from Figure 7(a) that the inrush current and capacitor stresses are less when compared to other three novel arrangments at similar boost factor. In Figure 7 (b), due to its structure the stress across C1 is increased. The capacitor C2 stress is increased in Figure 7 (c), but this stress is decreased to some extent in Figure 7 (d). Therefore, type-1 shown in Figure 7 (a) is taken as an example to extract other simulation results. In shootthrough state, D3 and D4 are conducting; consequently, the voltage across them is zero. Likewise, during nonshoot-through, the diode Din, D1, and D2 are conducting state; therefore, the voltage across them is also zero. The steady-state peak DC-link voltage, and currents through inductor, diode Din, and DC-link repectively are shown in Figure 8 (b). The dc-link voltage is zero in shoot-through state due to short across the inverter bridge and is peak value of about 395 V in non-shoot-through state. The inductor current is increasing in shoot-though state which implies that the inductors are charging, in non-shoot-though state, the current flowing through inductor is decreasing in order to discharge the inductors. As portrayed in bottom of Figure 8 (b), the dc-link current which is similar as input current and is discrete. In case of SBC, in zero-state, the current is zero and during shoot-though and active states the current is non-zero. Therefore, to avoid discontinuous in the input current, maximum boost control method can be used [25] in which all the zero states are used as shoot-through states and also increases the voltage boost.

Experimental results
To validate the simulation results, the experimental test is conducted in the laboratory with the same parameters. The input voltage along with DC-link voltage and diode voltages are depicted in Figure 10 (a). The peak DC-link voltage and diode D1 voltages are boosted to 382 V and 285 V respectively. The diode D3 voltage is boosted to 89 V in non-shoot-through state and is almost zero in shoot-through state. Figure 10 (b) shows the steady-state capacitor C1, C2, C3, and C4 voltages. From these figures it is seen that due to drop across the diodes, inductors and switches; the experimental values are slightly less when compared to simulation values. Figure 11 (a) depicts the inductor L1 and L3 currents along with input Iin and diode Din currents. It is observed that the inductor currents are increasing linearly in shoot-through state and it is decreasing linearly in non-shoot-through state, which represents charging and discharging of the inductors respectively. It can be seen from this figure that the input current (same as dc-link current) is zero during zero state and it is nonzero in other states (i.e., during shoot-through state and active states). Figure 11 (b) depicts the phase voltages (i.e., Van, Vbn, and Vcn) of three-phase system at M = 0.75888. The line voltage, phase voltage and the phase current are also obtained in Figure 11 (c) and it seen that the magnitude of voltages are less when compared to simulation and theoretical values.

CONCLUSION
This paper presents a new family of four different configurations of enhanced-boost quasi-Z-source inverters which provides discrete input current. The projected configurations provide very high voltage boost at high modulation index which results into high quality waveforms. Moreover, these configurations share common ground with input source and VSI bridge to diminish leakage current problem. In addition, the proposed topologies reduce the capacitors stress and inrush current problem. Among all these four proposed topologies, type-1 DIC EB-qZSI has more advantage, like less inrush current and less capacitor stress. The steady-state process, and the derivation of boost and capacitor voltages are given for both continuous and discontinuous conduction modes. The simulation and experimental test results have been verified with the theoretical expressions.