Implementation of Space Vector Modulator for Cascaded H-Bridge Multilevel Inverters

Abstract

The Space Vector Modulation (SVM) technique has gained wide acceptance for many AC drive applications, due to a higher DC bus voltage utilization (higher output voltage when compared with the SPWM), lower harmonic distortions and easy digital realization. In recent years, the SVM technique was extensively adopted in multilevel inverters since it offers greater numbers of switching vectors for obtaining further improvements of AC drive performances. However, the use of multilevel inverters associated with SVM increases the complexity of control algorithm (or computational burden), in obtaining proper switching sequences and vectors. The complexity of SVM computation causes a microcontroller or digital signal processor (DSP) to execute the computation at a larger sampling time. This consequently may produce errors in computation and hence degrades the control performances of AC motor drives. This paper presents a developement of SVM modulator for three-level Cascaded H-Bridge Multilevel Inverter (CHMI) using a hybrid controller approach, i.e. with combination between the DS1104 Controller Board and FPGA. In such way, the computational burden can be minimized as the SVM tasks are distributed into two parts, in which every part is executed by a single controller. This allows the generation of switching gates performed by FPGA at the minimum sampling time 〖DT〗_2=540 ns to obtain precise desired output voltages, as can be verified via simulation and experimental results.