Simulation design and analysis 9-level H-bridge single phase stepdown cyclo inverter

ABSTRACT


INTRODUCTION
AC to DC converter, better known as an inverter, is a type of power electronics circuit that has been widely used in the community.Its presence is mostly required for control of power equipment.In general, inverters have a square-shaped output wave format, so by engineering the input DC voltage from several levels, the output shape will resemble a sinusoidal wave.This concept is more popular with the multilevel inverter method (MLI).The H-bridge multilevel inverter is an appropriate alternative solution choice among the existing multilevel inverter topologies [1].This multilevel inverter is generally used as a three-phase induction motor rotational speed controller that requires v/f adjustment using a pulse width setting (PWM) technique [2].The more the number of levels, the MLI output waveform is closer to the sinusoid so that it will decrease the THD.However, this increase in voltage level is accompanied by disadvantages, among others, that this inverter requires a larger number of switches, a more complicated control system, and a higher cost [3].MLI can be built using a combination of power semiconductor devices such as MOSFET, and IGBT where the MLI voltage format is in the form of a step-step voltage wave pattern resulting from a predetermined gate switch sequence setting [4], [5].IGBT is a semiconductor device that is often used in cycloconverter circuits in high-speed and high-frequency induction motor control operations [6].The inverter voltage source can be a battery, solar power, or other DC voltage source.The multistage inverter is composed of several single-phase H-Bridge inverters 2265 connected in series [7], [8].MLI is very suitable for high voltage applications, because it has high efficiency, better power quality, small switching losses, decreased magnetic interference, and close to one power factor.However, it is rather difficult to operate in quadrant 4 in the energy conversion process and the Hbridge inverter can cause voltage spikes on the output side [9]- [11] so that the MLI still contains harmonic components on the output side of the waveform in the form of non-sinusoidal.In low-power applications, this non-sinusoidal voltage spike can still be tolerated, but for high-power applications, the presence of harmonics is a serious problem that requires handling [12].Important things to consider in designing an MLI are the use of a minimum number of switches and a DC source voltage, a simple drive circuit, and low cost.Inverter output voltage regulation can be done using PWM control.This method is very efficient and effective where the DC source voltage is fixed while the output voltage is regulated through the ON-OFF period of the inverter switch [13].There are three basic topologies for multilevel inverters, including diode clamped MLI, flying capacitors MLI, and cascaded H-bridge MLI [14].Inverter classification can also be categorized into two types, namely inverters with symmetrical and non-symmetrical topologies.The first type of topology has an identical source voltage level while the non-symmetrical type has a voltage input with different amplitude, number of switches, and switching sequences so that the topological modularity remains incomplete [15], [16].On the other hand, harmonic disturbances can occur in the power system when the first AC system is created [17].The trigger angle of the inverter switch gate requires precise considerations and calculations so that a small THD index can be obtained.There are various kinds of control for inverters, one of the simplest control methods is sinusoidal pulse width modulation (SPWM) [18], [19].The SPWM-based method is the right way to reduce THD in a multilevel inverter gate switch because it has a better dynamic response and small commutation load with reduced switching losses [20] .Some other applications of this inverter are to control the speed regulation of induction motors [21] and as an intermediary in the power grid between renewable electrical energy (PV) generators and power plants [22].Cyclo inverter is another type of power electronics circuit that has a working pattern of converting fixed frequency AC power into variable frequency AC power format [23] the output frequency of the cyclo converter can be greater or less than the input frequency [24].The cyclo converter consists of converter P and converter N arranged in parallel.The frequency of the output waveform can be adjusted by varying the number of cycles of the converter P in the positive period and the converter N in the negative cycle.The number of cycle variations as an integer multiple of the input frequency.Cyclo inverter is widely used as an induction motor drive from small to a large power.
Research related to cyclo inverters is still rarely done.The author only found a few articles but the most recent one was about four years ago.So that this research needs to be developed in order to find new discoveries.Several previous researchers, including Mayank Kumar, made a soft switch for a single-phase cyclo inverter switch based on IGBT which resulted in a change in the input frequency voltage into an output voltage at a high frequency to improve device performance compared to the use of PWM [25].Sudhin Govind engineered a cyclo inverter for controlling a high-power single-phase induction motor using an IGBT semiconductor switch where the output is an integer multiple of the input frequency.This paper describes the development of a single-phase cyclo inverter by inserting 9-levels of IGBT H-bridge Inverter through modeling simulation using the Simulink MATLAB tool.

METHOD
This research work was carried out through several stages.The workflow is shown in Figure 1. Figure 1 is the flow of the research method that is being carried out.The first step is to collect literature from various library sources to deepen knowledge related to cyclo inverters.The second stage is to design the concept of a 9-level cascade H-bridge and a cyclo inverter using an IGBT semiconductor device with an input voltage of 9 volt for each step electronically.The next step is to build an electronic design modeling design into the MATLAB/Simulink tool accompanied by a model of the trigger pulse generator circuit for the two circuits.The next stage is testing and observing a circuit of models by running the model on a MATLAB application.The test results were then analyzed and compared with the literature and concluded as the last step.The number of bridge inverters can be determined by (m-1)/2 where m is the number of inverter levels.Each inverter bridge circuit has an output voltage of +VDC, 0, and -VDC.Thus, the maximum output voltage value is 9×48 Vpp (volts peak to peak).The performance of each H-bridge inverter can be regulated by the gate pulse on each switch.The second part is a cyclo converter circuit consisting of a P (Positive) converter and an N (Negative) converter which is connected in parallel with the load.The P converter is an arrangement of bridge rectifiers using silicon-controlled rectifier (SCR) to carry the input current in the positive cycle, while the N converter consists of a bridge rectifier circuit in the opposite direction to the P converter.This N converter plays a role in flowing input current in the negative cycle.The pattern and waveform of the output current depending on the pulse settings on each switch of the P converter and the N converter.The trigger pulse of the P converter and N converter will change the input frequency of the 9-level inverter to a lower and varied frequency.The third and fourth parts are the trigger pulse generator for 9-level inverter performance with a pulse width modulation (PWM) pulse generator while the cyclo converter circuit trigger pulse uses a pulse width setting.
Figure 3 is a modeling system from Figure 2 using MATLAB/Simulink tools.The bridge circuit is arranged in series with the input voltage of each switch of 48 volts.The switch of each bridge has four trigger gates (G1-G4) first level, (G5-G8) second level, (G9-G12) third level, and (G13-G16) in the fourth level.

RESULTS AND DISCUSSION
In this section, it is explained the results of the research and at the same time is given the comprehensive discussion.Results can be presented in figures, graphs, tables, and others that make the reader understands easily.The discussion can be made in several sub-sections.

9-level inverter gate trigger pulse generator
The inverter's 9-level switch cascade performance is activated by PWM pulses.There are two kinds of PWM pulse width modulation techniques, namely phase shifted PWM (PS PWM) and level-shifted PWM (LS PWM).PS PWM uses several triangular carrier signals that have the same amplitude and frequency but there is a phase shift between the carrier waves.The number of carrier signals with n levels required is (n-1).While the phase shift can be determined at (360 0 /n-1).The PWM gate pulses are obtained from the proper comparison of the carrier signal and the triangular signal as well as the modulating signal.Level-Shifted PWM (LS PWM) also requires a number of triangular carrier signals but is applied at different levels.This type of modulation produces a smaller THD.
Figure 4 is an LS PWM pulse generator by modulating a sinusoidal signal on a triangular carrier signal with a frequency of 200 Hz.There are 16 gate switch inverters (G1-G16) that must be activated with a gate pulse so that it requires 8 (eight) triangular carrier waves at the same amplitude and frequency but the carrier signals are set at different levels.Using a sinusoidal wave comparator compared to the carrier signal will produce an output wave pulse with a PWM-controlled pulse width.The inverting circuit is mounted on the output side so that two pulse signal patterns of opposite levels are obtained to activate the switch pair.In the Simulink application, the sequence of the carrier waves for each pulse generator for switching on is declared as the time value and output value.The time value of all carriers is set to the same value, namely 0 2.5e-3 5e-3.The output value can be seen in Table 1.Table 1 lists the repeating sequence carrier waveform levels used to generate PWM pulses for the four H-bridge switches.The results of the pulses generated are shown in Figure 5.
Figure 5 is a series of 9-level inverter gate switching pulses G1 -G16.The pulse has an amplitude of 1 volt, and a frequency of 200 Hz, with the pulse width for each switch varying.The switch pairs of each inverter level are triggered by pulses that are complementary or opposite logic.For example, in pair G1 and G2, when switch S1 is triggered by pulse G1 logic high (1) then switch S2 is activated with pulse G2 in logic low (0).And so on for the G3 and G4, G5 and G6 pairs, and other switch pairs.

Gate trigger pulse generator and cyclo inverter switch performance
Generally, a cyclo inverter converts a sinusoidal input with a fixed frequency into an AC wave with a variable frequency.However, in this study, the cyclo inverter circuit gets input in the form of a ladder voltage that comes from the output voltage of the IGBT 9-level inverter unit.The inverter functions as a controlled bridge rectifier.The P inverter operates in the positive half-cycle rectifier process and the N inverter acts to flow current in the negative half-cycle.The bridging switch on the cyclo inverter P (S17, S18, S19, S20) inverter circuit is triggered using an A1 trigger pulse while on the N inverter (S21, S22, S23, S24) it is activated with A2 pulses.There are two modes of cyclo inverter performance, namely the mode when the P inverter is ON then the inverter N is OFF and the second mode is when the N inverter turns ON and the P inverter turns OFF.As shown in Figure 6(a), the working principle is when the cyclo inverter gets a positive cycle input voltage from a 9-level voltage source, current flows through the switch S17, the load RL, S20 then returns to the source (in according to arrowed dash line).The S18 switch is useful for blocking the input current from being connected directly to the P inverter and diverting the input current to pass through the S17 switch.While switch S19 is needed to block the current from switch S17 so that it does not go to the source because a short circuit will occur, but the current has flowed to the load and back to the source.So, on Figure 6(b) when working on a negative cycle, the input current will flow through S22, Load RL, S23, and back to the source.S24 is used to block the flow of current from S22 so that it does not return directly to the source but is transferred to the load and then through S23 the current returns to the source.2 shows the timing of the trigger signal periods A1 and A2 for each 1/n divider of the cyclo inverter.
The average voltage value of one cycle on n (4).
The value of the effective stress (rms) one cycle can be determined by the (5).   3 is the condition of the switch (S1 -S16) when it is at the positive cycle level, level 0 and negative level.The battery voltage for each inverter is 48 volts, so the lowest level is at -192 volts and the highest level is 192 volts.The zero point of the voltage is at level five.The multilevel inverter ladder wave is designed to resemble a sinusoidal wave, but in reality, the wave still has distortion so it is not pure sinusoidal.Figure 10(a) is the THD index value of the 9-level output voltage waveform of 14.33% which states the shift of the output waveform to the sinusoidal shape.Figure 10(b) is the THD index of the voltage divider at a frequency of 25 Hz cyclo inverter of 65.64%.This value is quite high because the resulting waveform is still far from a sinusoidal shape.Figure 10(c) is a cyclo inverter three divisor THD index value of 73.72%.Similar to the previous divisor THD index value, the THD value increases because the output waveform shift does not resemble a sinusoidal waveform.This is because the form factor of the input waveform is not sinusoidal and already contains a large harmonic index.So, to lower the THD index, a filter that is tuned at the right frequency is needed so that the harmonic value is low.

Figure 1 .
Figure 1.System design research flow

Figure 4 .
Figure 4. LS PWM Sinusoidal modulation and triangular carrier signal

Figure 6 .
Figure 6.Power flow of cyclo inverter on (a) positive mode (b) negative mode

Figure 9
Figure9(a) is a cyclo inverter divider (divider of two) waveform which has two ladder waves of four levels of a 9-level half-wave cyclo inverter on a positive cycle and two ladder waves of four levels of a halfwave cyclo inverter on a negative cycle.One period (T) of the wave is 0.04 s so that the frequency of the wave (1/T) is 25 Hz.Figure9(b) describes the same conditions in the cyclo inverter triple divider, the output wave pattern appears three 4-level cyclo inverter half-wave signals in the positive cycle and three 4-level cyclo inverter halfwave signals in the negative cycle.One wave cycle takes T = 0.06 ms so that the frequency of the cyclo inverter output waveform can be determined (1/T) of 16,667 Hz.Thus, it can be said that for the n-th frequency divider of a cyclo inverter, at the output voltage there will be n integer multiples of the cyclo inverter half-wave signal in the positive cycle and n cyclo inverter half-wave signals in the negative cycle.

Figure 9 (Figure 9 .
Figure9(a) is a cyclo inverter divider (divider of two) waveform which has two ladder waves of four levels of a 9-level half-wave cyclo inverter on a positive cycle and two ladder waves of four levels of a halfwave cyclo inverter on a negative cycle.One period (T) of the wave is 0.04 s so that the frequency of the wave (1/T) is 25 Hz.Figure9(b) describes the same conditions in the cyclo inverter triple divider, the output wave pattern appears three 4-level cyclo inverter half-wave signals in the positive cycle and three 4-level cyclo inverter halfwave signals in the negative cycle.One wave cycle takes T = 0.06 ms so that the frequency of the cyclo inverter output waveform can be determined (1/T) of 16,667 Hz.Thus, it can be said that for the n-th frequency divider of a cyclo inverter, at the output voltage there will be n integer multiples of the cyclo inverter half-wave signal in the positive cycle and n cyclo inverter half-wave signals in the negative cycle.

Figure 10 .
Figure 10.THD index value of (a) output voltage 9-level inverter; (b) voltage divider of two cyclo inverter (c) cyclo inverter triple voltage

2268 Table 1 .
PWM pulse generation carrier wave level

Table 2 .
Period,   and THD at each frequency of the cyclo inverter output voltage

Table 3 .
Voltage level when cyclo inverter operates on positive cycle and negative cycle