Biopotential multi-path current feedback instrumentation amplifier with automatic offset cancellation loop for resistive bridge microsensors

ABSTRACT


INTRODUCTION
Micro-electro-mechanical systems (MEMS) technology is currently gaining significant attention due to the inherent advantages of miniaturization, high signal-to-noise ratio (SNR), and affordability, which has led to its ubiquitous application across a plethora of sensing devices [1].Among these, resistive MEMS sensors stand out, offering a unique combination of structural simplicity, superior linearity, and robust durability, making them an optimal choice for the detection of various data, including but not limited to biological signals [2]- [6].
Additionally, MEMS resistive sensors require a change to detect an amount of physical change.This resistive change converts to a low amplitude voltage [7], [8].For this reason, a good use for MEMS resistive bridge sensors in electromyogram (EMG), electrocardiogram (ECG) and electroencephalogram (EEG) biopotential signals, is an instrumentation amplifier with high precision signal processing low noise thanks to its high gain and CMRR also, thus eliminating offset voltages by an automatic offset cancellation circuit [9].
The amplitude of biopotential signals typically lies within a minute range of about 5 µV to 20 mV, and these signals operate within the frequency domain of 0 Hz to 1 kHz [10].As such, the main objective in designing an instrumentation amplifier for these signals is to prioritize the achievement of low noise, minimal power usage, and enhanced input impedance [11].When it comes to quantifying energy efficiency and evaluating the trade-off between power consumption and noise in biomedical devices, the Noise efficiency factor (NEF) often serves as the standard measure [12].It is calculated as in (1). = ₙᵢ͵ᵣₘₛ √ 2ₜₒₜ .ᴛ.4.(1) Where Vₙᵢ͵ᵣₘₛ is the input referred noise voltage (IRN), Iₜₒₜ is the current, Uᴛ is the thermal voltage, k is Boltzmann's constant, T is the temperature in Kelvins (body temperature =300 K), and BW is the bandwidth of the system in Hz.
The capacitively coupled instrumentation amplifier (CCIA) plays a significant role in precise biopotential measurements.Its purpose is to eradicate DC offset at the electrode-skin interface, effectively blocking undesired potential signals.However, it's worth noting that the CCIA's input impedance is adversely affected by its input capacitance, which results in a lower impedance.As the chopper's frequency escalates, this problem can trigger a decrease in signal amplitude and a reduction in the common-mode rejection ratio (CMRR), consequently influencing measurement precision [13].A noteworthy correlation can be drawn between the input capacitance of the CCIA and the input impedance.
The current feedback instrumentation amplifier (CFIA) incorporates an input transconductance stage [14], setting it apart from alternate amplifier configurations and contributing to its potential for attaining a high common mode rejection ratio (CMRR) [15].The CFIA achieves high input impedance effectively by utilizing the gate input capacitance of the input transconductance (Cg).This capacitance includes parasitic capacitors (Cp1, Cp2, and Cp3), coupled with the switched-capacitor (SC) resistor (CH1) of the input chopper.The combined effect of these components plays a crucial role in determining the final input impedance.2109 amplification necessitates the matching of Gm1 and Gm2, as stipulated in [16].Techniques aimed at reducing noise are vital in fabricating a neural signal amplifier, having the potential to curb the flicker noise that leads to a decrease in biopotential signals emanating from resistive bridges.Two notable strategies-chopper stabilization (CHS) and automatic zeroing (AZ) -have been identified as effective means to attenuate the impact of noise density and DC offset in the baseband, as referenced in [17].

𝑍ᵢₙ(𝐶𝐹𝐼𝐴) =
In our research, we introduce a unique analog front-end (AFE) configuration, specifically designed for resistive bridge microsensors.The emphasis in this proposed AFE is on minimal power consumption and noise reduction, achieved by incorporating a chopper-stabilized multipath current-feedback class-AB CFIA and an automatic offset cancellation loop developed.The CFIA applies chopper stabilization methods to effectively reduce offset and 1/f noise.Additionally, the incorporation of a ripple reduction loop (RRL) aims to diminish output ripple.To evaluate the AFE's performance, we built and simulated it using a 180 nm CMOS technology framework and powered it with a 1.8V power supply.
The rest of the parts of the paper are organized as follows: i) Section 2 gives an overview of the resistive bridge AFE design as well as the architecture and sub-blocks; ii) Simulation results and comparisons are described in section 3; and iii) Finally, the conclusion and upcoming work are discussed in section 4.

DESIGN AND METHOD 2.1. Overall circuit design
In the field of biomedical signal measurements, the sensitivity of sensors is paramount.They need to be capable of accurately and precisely gauging weak signals while mitigating distortion.In light of this, crafting an appropriate analog front end (AFE) becomes crucial to ensuring high-quality readings.This paper takes cues from previous work [18] to construct a low-noise AFE specifically designed for resistive bridge microsensors.The proposed AFE circuit's topology, depicted in Figure 2, incorporates several components: a multipath CFIA, a 2nd-order low-pass filter (LPF), a buffer, a 12-bit successive approximation register analogto-digital converter (SAR-ADC), and an automatic offset cancellation loop (AOCL) that features an R-2R digital-to-analog converter (DAC).
The advanced fully differential CFIA under discussion has the capacity to augment the input signal transmuted by the resistive bridge in the first stage.The output stage of the CFIA might encounter an undesired offset from the resistive bridge amid the amplification process.Hence, an AOCL circuit is employed to rectify the external offset originating from the mismatch of the bridge.Internal offsets within the HFP are maintained stable by a high-gain LFP amplifier and a low noise chopper amplifier.To mitigate the output fluctuation engendered by the up-modulated DC offset in the LFP, the employment of an AC-coupled RRL [15]- [18] is seen as a viable strategy.

Proposed multipath current feedback instrumentation amplifier
The structure of the multipath CFIA is composed of two primary channels -the low frequency path (LFP) and the high frequency path (HFP), as represented in Figure 3.In order to mitigate the effects of 1/f noise and DC offset within the baseband, the LFP employs the CHS technique [19], whereas the RRL is incorporated to restrain the up-modulated ripple.For the purpose of maintaining stability in the CFIA at lower frequencies, Cm2 is introduced to the multipath in conjunction with the compensation capacitors Cm, thereby equating Cₘ₂ with Cₘ₁.The frequency value at unity gain is.
At the DC operating point, Gm11 = Gm21 = 156 μA/V and Cm51 = 49 pF, so the UGBW is 506 kHz.The LFP consists of five stages this is why its gain is very large compared to the gain of HFP, to obtain an offset-stabilized for the latter which has a residual offset at the input (Gm11).According to (6), we need to strengthen the LFP's gain in order to remove the HFP's offset, therefore Gm3 is designed as a gain-boosted single-stage folded-cascode OTA to reinforce the DC gain and bring down the HFP's offset to 1 µV [15].The residual input offset can be expressed as (6) [20].
Vos,ᵢₙ here refers to the offset of Gm11.Internal offset stabilization is achieved by transmuting the offset voltage Vos21 into a current, denoted Ios21, at the output of Gm21.This current, once rippled by CH3 modulation, is transformed into a triangle-wave voltage, symbolized by (V), via a Miller integrator (Gm3).Interestingly, the ripple at the output of Gm3 can be represented as (7).The ripple voltage at Gm3's output will be integrated once again by Gm5 as a sinusoidal ripple at the CFIA's output, and its amplitude may then approximately be estimated using (8).The high frequency ripple of the converted voltage generated at the output of Gm3 is sensed, demodulated and converted into a compensation current by the RRL with good impact, which consists of an input AC coupling capacitors Cs, a current buffer (CB), a CLPF capacitor to mitigate the RRL's second-harmonic ripple when using with output impedance of a current buffer (CB), and a transconductance Gm6.The ripple voltage is transformed by Cs into the current IR, which CH4 then demodulates into DC.The current at the input of CB is given by (9).

𝑉𝑅𝑖𝑝𝑝𝑙𝑒, 𝑜𝑢𝑡 ≈ 𝑉𝑅𝑖𝑝𝑝𝑙𝑒
As a result, the current, referred to as IR, at the CB's output can be estimated as presented in (10).Here, VCB signifies the output voltage of CB, RCB stands for the DC output impedance of CB, and ACB represents the DC voltage gain of the NMOS cascode in CB.
Accordingly, to enhance ripple suppression, the CB is mounted as a gain-boosted Current Buffer.The two output currents of Gm21 and Gm22 merge with the output current of Gm6 (ripple) in (11) (11) The voltage without ripple is transformed to a current through Gm4 and is mixed with the HFP currents and integrated through Gm5.As a result, the ripple is reduced more effectively.The design of current buffer (CB) with in RRL [15] is shown in Figure 4.
The suggested block diagram of the CFIA circuit with feedback can be seen in Figure 5, which is adopted an AC-coupled capacitive feedback network with a parallel pseudo-resistor, in hopes of reducing the chip area and give the low-frequency attenuation properties.We may create a high-pass transfer function using the capacitive feedback [21].The transfer function of the CFIA can be expressed as (12) without the compensation voltage of DAC.The SPI enables gain adjustments via a 5-bit programmable weighted capacitor array, CF1, facilitated by controlling each switch within the capacitor array.The range for this programmable gain spans from 20 dB (00000) to 55 dB (11111).The multipath CFIA utilizes a chopping frequency of 75 kHz, synchronized with the non-overlapping clocks.
The detailed representation of the HFP within the suggested CFIA is provided in Figure 6(a).This configuration includes a class-AB output stage, Gm5, along with non-chopped input trans conductors Gm11 and Gm12.The currents transitioned via the trans conductors stages Gm11, Gm12, and Gm4, are combined by an active Miller-compensated class-AB output stage Gm5 [22].At the Gm5 juncture, the class-AB biasing and elevation of power efficiency is executed through a Monticelli-style floating setup using MP14, MN5, MP15, and MN6.Notably, this Monticelli style is also crucial in curbing signal distortion [23].The addition of an error amplifier CMFB circuit in the HFP assists in managing the bias current of the cascode stages, thereby ensuring a higher differential output range with minimal power consumption [24].Figure 6(b) showcases the CMFB.To compensate for the frequency response within the HFP, a nested Miller compensation technique is employed [25].
It's important to note that the input referred noise (IRN) of the CFIA is predominantly influenced by the LFP and input stage of the HFP.The IRN dominated by the HFP's input stage, inclusive of thermal and flicker noise components, can be approximated as (13).

Suggested automatic offset calibration loop circuit design
In response to the offset issue that emerges from the amplification of the resistive bridge sensor at the CFIA's output stage, an automatic offset calibration loop circuit (AOCL) is proposed.The aim of this circuit is to alleviate the unwanted offset [26].
The AOCL comprises a comparator, a 12-bit successive approximation register (SAR) logic module, and a 12-bit R-2R digital-to-analog converter (DAC) [27], as illustrated in Figure 7.During the calibration process, the comparator evaluates the amplified offset that stems from the bridge at the CFIA output node.The result from the comparator then triggers the 12-bit SAR logic, which in turn generates a 12-bit digital control signal intended for the DAC.This signal is subsequently inputted into the 12-bit R-2R DAC [18]- [27].Consequently, the DAC produces the necessary voltage for offset correction.A Dynamic Comparator was employed in our design, which makes use of a StrongARM latch architecture, to evaluate the amplified bridge offset at the CFIA output node.The StrongARM latch structure, as represented in Figure 8, shows power efficiency and reduced offset.This design includes a differential pair input, two sets of cross-coupled transistors M3-M6, four clocked PMOS switches S1-S4, and an SR-latch.The SR-latch is responsible for latching the differential outputs and generating VCOMP_OUT.The offset impact of transistors M3-M6 is reduced by deactivating them initially through the pre-charging operation of PMOS switches S1 to S4 [28].This feature provides the StrongArm architecture with increased offset compensation resilience.
Within the AOCL, the 12-Bit SAR control logic is organized around two sequences of edge-triggered D flip-flops, which sequentially determine each bit.Each D flip-flop is engineered with a transmission gate (TG) and inverters.The first sequence of flip-flops operates as a shift register, receiving data from the comparator.On the other hand, the second sequence of flip-flops functions as a data storage module, with the responsibility of generating the DAC control input, as shown in Figure 9  The layout of the R-2R DAC circuit is presented in Figure 10.We employ an R-2R ladder network to enhance precision, albeit at the expense of increased area requirements.The resistors are linked either to a high voltage or to the ground, mediated by a transmission gate.This gate amalgamates a PMOS and an NMOS, with their gates connected to the incoming voltage and their drains merged at a common node.A particular challenge that arises in designing an R-2R DAC is maintaining monotonicity [30].This is manifested when an increase in the input could potentially result in a decrease in the output.One approach to mitigate this issue involves minimizing the resistance of the transmission gate, achieved by widening it to facilitate smoother current flow within the circuit.

RESULTS AND DISCUSSION
The analog front end (AFE) was both simulated and implemented in Cadence using TSMC's 0.18μm technology.It was designed to operate at a supply voltage of 1.8V, consuming only 291 μW of energy, with a total bias current of 162 μA. Figure 11 depicts the measured transfer function of the current feedback instrumentation amplifier (CFIA).The AFE incorporates a multi-path chopper stabilized architecture to mitigate notches caused by the amplifier's transfer function within the chopper frequency band.As a result, the bandwidth is expanded while maintaining a low noise performance [31].It is evident from the measurements that a gain of 50.77 dB is achieved within the 0.1-1.5 KHz bandwidth.Figure 12 illustrates the programmable gain settings, ranging from a gain of 20.35 dB for (<DIN> = 00000) up to 55.14 dB for (<DIN> = 11111).The unit gain bandwidth (UGBW) is measured at 500 kHz, and the phase margin at UGBW is 77.5°.These results demonstrate that the AFE effectively amplifies weak signals from the resistive bridge sensor while minimizing noise interference.
Figure 13 and Figure 14 show the measured CMRR and PSRR, which report 114 dB and 103 dB respectively over the range of 0.1 to 100 Hz. Figure 15   Once the AOCL operation begins, the initial offset is quickly corrected.In the absence of the acceleration capacitor Cv, the offset calibration time amounts to 11 ms.However, when Cv is implemented, it can be seen that the offset calibration time for the AOCL operation drops to 5 ms, as illustrated in Figure 18.To ascertain the circuit's resilience in relation to offset fluctuations, we conducted a Monte-Carlo simulation with 200 samples.Figure 19, showcasing the simulation of the variation in input referred offset, reveals the average value of the input referred offset to be approximately 0.9 μV.The DAC outputs' DC operating point amid digital input variation is presented in Figure 20.
Using (1), it is calculated that the multipath CFIA's NEF is 5.18, leading to the energy efficiency factor (PEF), as given in (15) [32]. =  2 .ᴅᴅ (15) The performance comparisons between the proposed CFIA and many state-of-the-art IAs are summarized in Table 1.It may be deduced from [14], [18], [33], [34] that the recommended CFIA exhibits a good input-referred offset.It is possible to conclude that the suggested CFIA has better CMRR to reject the power-line interference at the output of CFIA.Although it may be noted that our circuit can operate over a better bandwidth with an important adjustment of the capacitor value while keeping a low power dissipation.

CONCLUSION
This study presents the development of an analog front-end (AFE) suitable for resistive bridge microsensors, created utilizing a 0.18 µm CMOS process.The system functions on a chopper-stabilized multipath framework, consuming a total current of 162 μA at a supply voltage of 1.8 V.The readout circuit comprises components such as a multi-path CFIA, AOCL, 2nd-order LPF, a 12-bit SAR ADC, a buffer, and an SPI block.The multi-path structure effectively eliminates the notches caused by the RRL, while the ripple resulting from chopper up-modulation is mitigated through the use of an RRL scheme in the LFP.The proposed circuit, by counteracting the offsets in the bridge, can facilitate low-noise performance.The AOCL component

Figure 4 .
Figure 4. Current buffer design Figure 5. Block diagram of the CFIA circuit with feedback

Figure 6 .
Figure 6.Schematic of the HFP circuit: (a) the high-frequency path in CFIA and (b) the CMFB circuit

2113 Figure 8 .Figure 9 .Figure 10 .
Figure 8.Strong arm latch topologies in AOCL displays the CFIA's transient response to a sine wave input with a 10-mV amplitude and a 1 kHz frequency.The total IRN of the CFIA is shown in Figure16, which indicates that the IRN is 70 ηV/√Hz at 1 Hz and 16 ηV/√Hz at 200 Hz.

Figure 11 . 2115 Figure 15 .Figure 16 .
Figure 11.Transfer function of the CFIA Figure 12.AC Programmable transfer function gain simulation results of CFIA

Figure 19 .Figure 20 .
Figure 19.Monte-Carlo simulation results of the input referred offset voltage to return negatively to the input of CH3.

Table 1 .
Measured performances summary and comparison