Nine-level inverter with lesser number of power semiconductor switches using dSPACE

Sumit Raj, Rajib Kumar Mandal, Mala De, Ashutosh Kumar Singh

Abstract


In this paper, a single-phase nine-level multilevel inverter (MLI) topology is created in which reduced number of switches, diodes and gate driver circuits can be used so as to obtain higher output voltage levels. Due to this configuration, the blocking voltage value across the switches will also get reduced. In this proposed single-phase MLI topology, increase in output voltage levels can be observed whenever there is increment in the number of switches in the configuration. Proper mathematical modeling and analysis of the voltage waveform of the proposed inverter have been done for a 9-level MLI. MATLAB platform is used for modeling and simulation of the MLI. Modulation index is varied in order to observe various outcomes through simulation. The proposed nine-level inverter configuration is experimentally evaluated in the laboratory for various modulation indices so as to validate the simulation results. Comparison of this topology is done with the classical MLIs in order to illustrate its advantages.

Keywords


DC-AC converter; multilevel inverter; sinusoidal PWM; total harmonic distortion;



DOI: http://doi.org/10.11591/ijpeds.v13.i1.pp%25p

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