Modified asymmetrical 13-level inverter topology with reduce power semiconductor devices

M Saad Arif, Zeeshan Sarwer, Shahrin Md Ayob, Mohd Zaid, Shahbaz Ahmad

Abstract


This paper introduces a modified multilevel inverter topology with asymmetrical dc sources combination. The significant features of the proposed circuit are the reduced number of switches and low total standing voltage (TSV). Proposed topology utilizes ten switches to produce 13 level output with per unit TSVp.u of 5.33. An additional feature of the proposed topology is the inherent negative level generation as there is no requirement of an H-bridge for the polarity reversals. Nearest level control (NLC) technique is used as the modulation strategy. Performance of the proposed topology is validated through extensive analysis using Simulink and PLECS software. Detailed circuit analysis and its power loss, as well as efficiency studies, have been carried out under constant and dynamic load conditions. Results obtained shows that the proposed topology is working well, producing an output of 13-level with total harmonic distortion of 6.36% and inverter efficiency of 98.8%. The topology is extended to n-level structure, and its generalized expressions for different parameters were formulated. The comparison of the generalized structure with other existing topology is carried out, and it is found that the proposed topology outperform other topologies on many parameters.

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DOI: http://doi.org/10.11591/ijpeds.v11.i4.pp2212-2222

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