A novel multilevel inverter with reduced components and minimized voltage unbalance

Ravi Ranjan Kumar, Jayanti Choudhary


Multilevel inverters are an emerging area of research in the field of power electronic circuits and applications. It has many advantages like near-sinusoidal output voltage, lower total harmonic distortion (THD), reduced dv/dt stress, lower peak inverse voltage (PIV) and so on. But there are some associated problems as well such as cost, size complexity, and capacitor unbalance voltage. Here a novel nine level inverter topology has been proposed which addresses the issue of high no of switching and capacitor voltage unbalance. The proposed system has numerous advantages. The cost, size and complexity are reduced and the voltage unbalance problem is solved. The voltage stress across the switches is also reduced. The power loss distribution among the switches is optimum. So, the efficiency of the system is improved. Hence the overall system performance is improved. The system performs well for varying load like resistive, inductive as well as motor load. The stator voltage speed control of a single-phase induction motor has also successfully been achieved. The pulse width modulation PWM technique has been used for producing the switching pulses. The complete simulation analysis of these systems has been realized using MATLAB software. A comparative analysis of this system with the recently proposed systems has been done which shows significant advantages in all the above mention areas.


Nine level inverters; Power loss distribution; Self-voltage balancing; Single voltage source; Total harmonic distortion

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DOI: http://doi.org/10.11591/ijpeds.v13.i4.pp2365-2377


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