Capacitor voltages balancing method for buck modular DC/DC converter

Firas Abdul-hadi Salih, Turki Kahawish Hassan

Abstract


The most critical problem of the modular DC-DC converter (MDCC) is the voltage balancing of the submodule (SM) capacitors, the MDCC with stepped 2-level modulation has been developed and presents a good solution, however, this type of modulation has many restrictions when there is a wide range of capacitance tolerance of the SM capacitors that results inaccurate capacitor voltages balancing. To solve this problem, this paper discusses a proposed method of capacitor voltage balancing. Compared with stepped 2-level modulation, the voltage balancing method using modified duty cycle modulation offers the merits: i) reduction in output voltage and SM capacitor voltages overshoot during dynamic operation and improvement in the time response of the system and; ii) accurate voltage balancing over wide range of capacitance tolerance of each SM capacitor; and iii) the sorting algorithm replaced with modified duty cycle modulation method for the SM capacitor voltages balancing which reduces the computation burden. The proposed method ensures a stable voltage balancing, improves the time response of the system, and decreases the voltage and current overshoot during the dynamic response compared with prior art of MDCCs, where the stepped 2-level modulation is adopted. An analytical simulation of the MDCC is presented using MATLAB/Simulink to explain the operation.

Keywords


DC/DC converters; Full bridge submodule; Half bridge submodule; HVDC systems; Modular multilevel converter; Pulse width modulation

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DOI: http://doi.org/10.11591/ijpeds.v13.i4.pp2277-2285

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