A carrier pulse width modulation for asymmetric three-level NPC inverter

Abstract

The three-level neutral point clamped (NPC) inverters are widely used in practice. One of nowadays research trends of multilevel inverter topologies has been reduction of switch number. For this aim, this paper presents an asymmetric three level NPC inverter and study on output performance of phase disposition (PD) carrier pulse width modulation (CBPWM) for different offset voltage functions. A MATLAB/Simulink model of three-level asymmetric NPC inverter is developed to examine the impact of varying the offset voltage on the CBPWM output performances. Total harmonics distortions factors (THD) of voltages and currents are investigated for the whole modulation indices range. The obtained results show that harmonics voltage contents would be advantageous to set in discontinuous pulse width modulation (PWM) methods, particularly at lower voltage range. For asymmetrical topology, simulation results show that switching frequency optimal (SFO)-PWM method has not good performance at low modulation indices and its harmonics content presents an improved at high modulation indices range. Finally, a comparison of the output voltage and current quality via THD index is made between the asymmetric three-level NPC circuit and the conventional three-level NPC circuit are also provided to evaluate the feasibility of the asymmetric three-level NPC inverter in applications.