Comparative Analysis of Different PWM Techniques to Reduce the Common Mode Voltage in Three-Level Neutral-Point-Clamped Inverters for Variable Speed Induction Drives

C. Bharatiraja, S. Raghu, Prakash Rao, K.R.S. Paliniamy

Abstract


This work presents the comparative study of the different PWM techniques to reduce the common-mode voltage (CMV) at the output of neutral point diode clamped inverter for variable speed drives. Here the comparative study is done by the phase opposition disposed (POD), sinusoidal pulse width modulation (SPWM), phase disposition (PD), phase shift (PS) space vector modulation (SVM) techniques are proposed. A good trade-off between the quality of the output voltage and the partial magnitude of the CMV is achieved in this work. The scheme is proposed for three-level inverter. This work realizes the implementation of Three-level diode clamped MLI for three-phase (Y-Δ) induction motor with the implementation of a space vector modulation technique without any additional control algorithm to reduce CMV within the range + Vdc/6. The Simulation with a 1HP induction motor drive system is setup in Matlab-2011b  and the same results validated effectively by hardware – FPGA-SPARTEN III processor and its shows that the CM voltage is effectively reduced and the maximum output voltage is not affected.

 DOI: http://dx.doi.org/10.11591/ijpeds.v3i1.1734


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