FPGA Based Design and Validation of Asymmetrical Reduced Switch Multilevel Inverter

C Bharatiraja, Harshavardhan Reddy, Sunkavalli Satya Sai Suma, N SriRamsai


This paper proposes a new Asymmetrical multilevel inverter topology with reduced number of switches. This topology is superior to the existing multilevel inverter (MLI) configurations in terms of lower total harmonic distortion (THD) value and lower cost. The idea incorporates a new module setup comprising of four different voltage sources having voltage output levels in a specific ratio. The proposed topology uses a novel pulse width modulation (PWM) technique (as presented) to control the gating pulses. The operation is simulated using MATLAB/SIMULINK and its results are validated through FPGA Spartan 3 based hardware prototype inverter (using three voltage sources to produce a 7 level output, which may be extended to 15 level). The circuit complexity is drastically reduced and it is suitable for medium and high power applications. THD for the output is quite low when compared with the conventional inverter.

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DOI: http://doi.org/10.11591/ijpeds.v7.i2.pp340-348


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