Voltage Ripple Reduction in Voltage Loop of Voltage Source Converter

Jedsada Jaroenkiattrai, Viboon Chunkag

Abstract


In order to achieve a good dynamical response of a full-bridge AC-DC voltage source converters (VSC). The bandwidth of PI controller must be relatively wide. This leads to the voltage ripple produced in the control signal, as known that its ripple frequency has twice of the line frequency and cause the 3rd harmonic of an input current. A Ripple Voltage Estimator (RVE) algorithm and Feed-Forward Compensation (FFC) algorithm are proposed and added to the conventional control. The RVE algorithm estimated the ripple signal to subtract it occurring in the voltage loop. As a result, the 3rd harmonic of the input current can be reduced, and hence the Total Harmonic Distortion of input current (THDi) are improved.  In addition, the FFC algorithm will offer a better dynamical response of output voltage. The performance evaluation was conducted through the simulation and experiment at 110Vrms/50Hz of the input voltage, with a 600 W load and 250 Vdc output voltage. The overall system performances are obtained as follows: the power factor at the full load is higher 0.98, the harmonic distortion at AC input power source of the converter is under control in IEC61000-3-2 class A limit, and the overall efficiency is greater than 85%.

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DOI: http://doi.org/10.11591/ijpeds.v8.i2.pp869-881

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