Design of a high-speed MCML D-Latch at 0.6 V in 45 nm CMOS technology

Sivasakthi Madheswaran, Radhika Panneerselvam


Metal oxide semiconductor (MOS) current mode logic (MCML) is generally preferred for high-speed circuit design. In this paper, a novel low voltage folded (LVF) MCML D-Latch is designed. The existing topologies of the MCML D-Latch consume more power and operate at 1 V. The proposed D-Latch can operate at 0.6V with better delay and power management. MCML circuits minimize delay and perform fast operations, hence it can be used in high-frequency applications. The proposed LVF MCML D–Latch is analyzed with the parameters such as power, delay, power delay product and output noise using cadence virtuoso in 45 nm complementary metal oxide semiconductor (CMOS) technology at a voltage of 0.6 V and a temperature of 27 °C. The proposed technique achieves 62.11% of power reduction, transient response speed improved by 51.23% and noise cancellation becomes 26.13% improvement over the existing circuit. It also achieves 96% of output swing which is more efficient compared to others. Finally, the parametric analysis is performed with different temperatures to verify the stability of the proposed circuit. From the simulated results, it is clear that the proposed LVF MCML D-Latch provides better performance in high-speed phase locked loop (PLL) applications.


D-Latch; low voltage folded D–Latch; MOS current mode logic; noise; power; propagation delay

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